SAK-XC161CJ-16F20F INFINEON [Infineon Technologies AG], SAK-XC161CJ-16F20F Datasheet - Page 68

• Manufacturer Part Number: SAK-XC161CJ-16F20F
• Description: 16-Bi t Single-Chip Microcontroller Preliminary
• Manufacturer: INFINEON [Infineon Technologies AG]

Preliminary
Variable Memory Cycles
External bus cycles of the XC161 are executed in five subsequent cycle phases (AB, C,
D, E, F). The duration of each cycle phase is programmable (via the TCONCSx
registers) to adapt the external bus cycles to the respective external module (memory,
peripheral, etc.).
The duration of the access phase can optionally be controlled by the external module via
the READY handshake input.
This table provides a summary of the phases and the respective choices for their
duration.
Table 17
Bus Cycle Phase
Address setup phase, the standard duration of this
phase (1
if the address window is changed
Command delay phase
Write Data setup / MUX Tristate phase
Access phase
Address / Write Data hold phase
Note: The bandwidth of a parameter (minimum and maximum value) covers the whole
Data Sheet
operating range (temperature, voltage) as well as process variations. Within a
given device, however, this bandwidth is smaller than the specified range. This is
also due to interdependencies between certain parameters. Some of these
interdependencies are described in additional notes (see standard timing).
2 TCP) can be extended by 0
Programmable Bus Cycle Phases (see timing diagrams)
64
3 TCP
Parameter Valid Values Unit
tp
tp
tp
tp
tp
AB
C
D
E
F
1
0
0
1
0
Timing Parameters
2 (5)
3
1
32
3
Derivatives
V1.0, 2002-03
XC161
TCP
TCP
TCP
TCP
TCP