SAK-XC2264-56F66L INFINEON [Infineon Technologies AG], SAK-XC2264-56F66L Datasheet - Page 42

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SAK-XC2264-56F66L

Manufacturer Part Number
SAK-XC2264-56F66L
Description
16/32-Bit Single-Chip Microcontroller with 32-Bit Performance
Manufacturer
INFINEON [Infineon Technologies AG]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SAK-XC2264-56F66L AC
Manufacturer:
Infineon Technologies
Quantity:
10 000
Preliminary
The XC226x also provides an excellent mechanism to identify and to process exceptions
or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware
traps cause immediate non-maskable system reaction which is similar to a standard
interrupt service (branching to a dedicated vector table location). The occurrence of a
hardware trap is additionally signified by an individual bit in the trap flag register (TFR).
Except when another higher prioritized trap service is in progress, a hardware trap will
interrupt any actual program execution. In turn, hardware trap services can normally not
be interrupted by standard or PEC interrupts.
Table 5
time:
Table 5
Exception Condition
Reset Functions
Class A Hardware Traps:
Class B Hardware Traps:
Reserved
Software Traps:
1) Register VECSEG defines the segment where the vector table is located to.
Data Sheet
Bitfield VECSC in register CPUCON1 defines the distance between two adjacent vectors. This table
represents the default setting, with a distance of 4 (two words) between two vectors.
System Request 0
Stack Overflow
Stack Underflow
Software Break
System Request 1
Undefined Opcode
Memory Access Error
Protected Instruction
Fault
Illegal Word Operand
Access
TRAP Instruction
shows all of the possible exceptions or error conditions that can arise during run-
Hardware Trap Summary
Trap
Flag
SR0
STKOF
STKUF
SOFTBRK
SR1
UNDOPC
ACER
PRTFLT
ILLOPA
Trap
Vector
RESET
SR0TRAP
STOTRAP
STUTRAP
SBRKTRAP
BTRAP
BTRAP
BTRAP
BTRAP
BTRAP
40
XC2000 Family Derivatives
Vector
Location
xx’0000
xx’0008
xx’0010
xx’0018
xx’0020
xx’0028
xx’0028
xx’0028
xx’0028
xx’0028
[2C
Any
[xx’0000
xx’01FC
in steps of
4
H
H
- 3C
Functional Description
H
H
H
H
H
H
H
H
H
H
H
H
1)
]
H
-
] [0B
XC2267 / XC2264
Trap
Number
00
02
04
06
08
0A
0A
0A
0A
0A
0F
Any
[00
7F
H
H
H
H
H
H
H
H
H
H
H
H
H
H
]
]
-
-
V0.1, 2007-02
Draft Version
Trap
Priority
III
II
II
II
II
I
I
I
I
I
Current
CPU
Priority

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