SAK-XC2264-56F66L INFINEON [Infineon Technologies AG], SAK-XC2264-56F66L Datasheet - Page 90

• Manufacturer Part Number: SAK-XC2264-56F66L
• Description: 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance
• Manufacturer: INFINEON [Infineon Technologies AG]

Preliminary
Variable Memory Cycles
External bus cycles of the XC226x are executed in five subsequent cycle phases (AB,
C, D, E, F). The duration of each cycle phase is programmable (via the TCONCSx
registers) to adapt the external bus cycles to the respective external module (memory,
peripheral, etc.).
The duration of the access phase can optionally be controlled by the external module via
the READY handshake input.
This table provides a summary of the phases and the respective choices for their
duration.
Table 21
Bus Cycle Phase
Address setup phase, the standard duration of this
phase (1 … 2 TCS) can be extended by 0 … 3 TCS
if the address window is changed
Command delay phase
Write Data setup/MUX Tristate phase
Access phase
Address/Write Data hold phase
Note: The bandwidth of a parameter (minimum and maximum value) covers the whole
Timing values are listed in
verified by characterization. They are not subject to production test.
Data Sheet
operating range (temperature, voltage) as well as process variations. Within a
given device, however, this bandwidth is smaller than the specified range. This is
also due to interdependencies between certain parameters. Some of these
interdependencies are described in additional notes (see standard timing).
Programmable Bus Cycle Phases (see timing diagrams)
Table 22
and
Table
88
23. The shaded parameters have been
Parameter Valid Values Unit
tpAB
tpC
tpD
tpE
tpF
XC2000 Family Derivatives
Electrical Parameters
1 … 2 (5)
0 … 3
0 … 1
1 … 32
0 … 3
XC2267 / XC2264
V0.1, 2007-02
Draft Version
TCS
TCS
TCS
TCS
TCS