HD6437101 RENESAS [Renesas Technology Corp], HD6437101 Datasheet - Page 147

• Manufacturer Part Number: HD6437101
• Description: 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

7.10
Internal I/O registers are accessed from the bus state controller, as shown in table 7.3.
Table 7.3
Internal Module SCI
Connected bus
width
Access cycles
Notes: 1. Converted to the peripheral clock.
7.11
One Bus Cycle: The bus is never released during a single bus cycle. For example, in the case of a
longword read (or write) in 8-bit normal space, four memory accesses to the 8-bit normal space
constitute a single bus cycle, and the bus is never released during this period. Assuming that one
memory access requires two states, the bus is not released during an 8-state period.
7.12
In this LSI, two words (equivalent to two instructions) are normally fetched in a single instruction
fetch. This is also true when the program is located in external memory, irrespective of whether
the external memory bus width is 8 or 16 bits.
If the program counter value immediately after the program branched is an odd-word (2n+1)
address, or if the program counter value immediately before the program branches is an even-word
(2n) address, the CPU will always fetch 32 bits (equivalent to two instructions) that include the
respective word instruction.
2. Converted to the system clock.
On-chip Peripheral I/O Register Access
Cycles in which Bus Is not Released
CPU Operation when Program Is in External Memory
Access to Internal I/O Registers
8 bits
2 cyc*
1
MTU,
POE
16 bits
2 cyc*
8 bits
Figure 7.10 One Bus Cycle
1
INTC
16 bits
2 cyc*
8 bits
bus is not released
Cycles in which
2
PFC,
PORT
16 bits
2 cyc*
8 bits
1
Rev.1.00 Sep. 18, 2008 Page 113 of 522
CMT
16 bits
2 cyc*
8 bits
Section 7 Bus State Controller (BSC)
1
A/D
8 bits
3 cyc*
1
WDT
16 bits
3 cyc*
REJ09B0069-0100
2
MMT
16 bits
2 cyc*
1