HD6437101 RENESAS [Renesas Technology Corp], HD6437101 Datasheet - Page 389

• Manufacturer Part Number: HD6437101
• Description: 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

12.3.2
One of four internal clocks (Pφ/8, Pφ/32, Pφ/128, Pφ/512) obtained by dividing the peripheral
clock (Pφ) can be selected by the CKS1 and CKS0 bits in CMCSR. Figure 12.3 shows the timing.
12.4
12.4.1
The CMT has a compare match interrupt for each channel, with independent vector addresses
allocated to each of them. The corresponding interrupt request is output when the interrupt request
flag (CMF) is set to 1 and interrupt enable bit (CMIE) has also been set to 1.
When activating CPU interrupts by an interrupt request, the priority between the channels can be
changed by means of interrupt controller settings. See section 6, Interrupt Controller (INTC), for
details.
12.4.2
The CMF bit in CMCSR is set to 1 by the compare match signal generated when CMCOR and
CMCNT match. The compare match signal is generated upon the final state of the match (timing
at which the CMCNT matching count value is updated). Consequently, after CMCOR and
CMCNT match, a compare match signal will not be generated until a CMCNT counter input clock
occurs. Figure 12.4 shows the CMF bit set timing.
Interrupts
Compare Match Flag Set Timing
CMCNT Count Timing
Internal
clock
CMCNT
input clock
CMCNT
Interrupt Sources
Pφ
N-1
Figure 12.3 Count Timing
N
Rev.1.00 Sep. 18, 2008 Page 355 of 522
Section 12 Compare Match Timer (CMT)
REJ09B0069-0100
N+1