HD6437101 RENESAS [Renesas Technology Corp], HD6437101 Datasheet - Page 308

• Manufacturer Part Number: HD6437101
• Description: 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 9 Watchdog Timer
Bit
5
4, 3
2
1
0
Notes: 1. Only 0 can be written after reading 1.
Rev.1.00 Sep. 18, 2008 Page 274 of 522
REJ09B0069-0100
Bit Name
TME
—
CKS2
CKS1
CKS0
2. Section 9.3.3, Reset Control/Status Register (RSTCSR), describes in detail what
3. The overflow interval listed is the time from when the TCNT begins counting at H'00
happens when TCNT overflows in watchdog timer mode.
until an overflow occurs.
Initial Value
0
All 1
0
0
0
R/W
R/W
R
R/W
R/W
R/W
Description
Timer Enable
Enables or disables the timer.
0: Timer disabled
1: Timer enabled
Reserved
These bits are always read as 1. The write value
should always be 1.
Clock Select 2 to 0
Select one of eight internal clock sources for input to
TCNT. The clock signals are obtained by dividing the
frequency of the system clock (
frequency for φ = 40 MHz is enclosed in
parentheses*
000: Clock φ/2 (period: 12.8 μs)
001: Clock φ/64 (period: 409.6 μs)
010: Clock φ/128 (period: 0.8 ms)
011: Clock φ/256 (period: 1.6 ms)
100: Clock φ/512 (period: 3.3 ms)
101: Clock φ/1024 (period: 6.6 ms)
110: Clock φ/4096 (period: 26.2 ms)
111: Clock φ/8192 (period: 52.4 ms)
TCNT is initialized to H'00 and count-up stops
TCNT starts counting. A WDTOVF signal or
interrupt is generated when TCNT overflows.
3
.
φ
). The overflow