M58BW032BB45T3T STMICROELECTRONICS [STMicroelectronics], M58BW032BB45T3T Datasheet - Page 13

• Manufacturer Part Number: M58BW032BB45T3T
• Description: 32 Mbit (1Mb x32, Boot Block, Burst) 3.3V Supply Flash Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

SIGNAL DESCRIPTIONS
See
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A19). The Address Inputs
are used to select the cells to access in the mem-
ory array during Bus Read operations either to
read or to program data to. During Bus Write oper-
ations they control the commands sent to the
Command Interface of the internal state machine.
Chip Enable must be Low when selecting the ad-
dresses.
The address inputs are latched on the rising edge
of Latch Enable L or Burst Clock K, whichever oc-
curs first, in a read operation.The address inputs
are latched on the rising edge of Chip Enable,
Write Enable or Latch Enable, whichever occurs
first in a Write operation. The address latch is
transparent when Latch Enable is Low, V
address is internally latched in an Erase or Pro-
gram operation.
Data Inputs/Outputs (DQ0-DQ31). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation, or are used
to input the data during a program operation. Dur-
ing Bus Write operations they represent the com-
mands sent to the Command Interface of the
internal state machine. When used to input data or
Write commands they are latched on the rising
edge of Write Enable or Chip Enable, whichever
occurs first.
When Chip Enable and Output Enable are both
Low, V
bus outputs data from the memory array, the Elec-
tronic Signature, the Block Protection Configura-
tion Register, the CFI Information or the contents
of Burst Configuration Register or Status Register.
The data bus is high impedance when the device
is deselected with Chip Enable at V
able at V
Down at V
on DQ0-DQ7 and DQ8-DQ31 are at V
Chip Enable (E). The Chip Enable, E, input acti-
vates the memory control logic, input buffers, de-
coders and sense amplifiers. Chip Enable, E, at
V
consumption to the Standby level.
Output Enable (G). The Output Enable, G, gates
the outputs through the data output buffers during
a read operation, when Output Disable GD is at
V
are high impedance independently of Output Dis-
able.
Output Disable (GD). The Output Disable, GD,
deactivates the data output buffers. When Output
Disable, GD, is at V
the Output Enable. When Output Disable, GD, is
IH
IH
. When Output Enable G is at V
deselects the memory and reduces the power
Figure 2., Logic Diagram
IL
, and Output Disable is at V
IH
IL
, Output Disable at V
. The Status Register content is output
IH
, the outputs are driven by
and
IL
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
or Reset/Power-
Table 1., Signal
IH
IH
, the outputs
, Output En-
IH,
IL
.
the data
IL
. The
at V
dently of Output Enable. The Output Disable pin
must be connected to an external pull-up resistor
as there is no internal pull-up resistor to drive the
pin.
Write Enable (W). The Write Enable, W, input
controls writing to the Command Interface, Input
Address and Data latches. Both addresses and
data can be latched on the rising edge of Write En-
able (also see Latch Enable, L).
Reset/Power-Down (RP). The
Down, RP, is used to apply a hardware reset to the
memory. A hardware reset is achieved by holding
Reset/Power-Down Low, V
Writing is inhibited to protect data, the Command
Interface and the Program/Erase Controller are re-
set. The Status Register information is cleared and
power consumption is reduced to the standby level
(I
data outputs are high impedance.
After Reset/Power-Down goes High, V
memory will be ready for Bus Read operations af-
ter a delay of t
t
If Reset/Power-Down goes Low, V
Block Erase, a Program or a Tuning Protection
Program the operation is aborted, in a time of t
RH
rupted.
During Power-up power should be applied simulta-
neously to V
When the supplies are stable RP is taken to V
Output Enable, G, Chip Enable, E, and Write En-
able, W, should be held at V
In an application, it is recommended to associate
Reset/Power-Down pin, RP, with the reset signal
of the microprocessor. Otherwise, if a reset opera-
tion occurs while the memory is performing an
erase or program operation, the memory may out-
put the Status Register information instead of be-
ing initialized to the default Asynchronous
Random Read.
See Table
and Power-up AC
Program/Erase Enable (V
Erase Enable input, V
venting Program and Erase operations from mod-
ifying the data. Program/Erase Enable must be
kept High (V
gram/Erase Controller is active, otherwise the op-
eration is not guaranteed to succeed and data may
become corrupt.
Latch Enable (L). The Bus Interface can be con-
figured to latch the Address Inputs on the rising
edge of Latch Enable, L, for Asynchronous Latch
PHWL
DD1
maximum, and data is altered and may be cor-
IL
). The device acts as deselected, that is the
, the outputs are high impedance indepen-
.
21
IH
DD
and
) during all operations when the Pro-
PHEL
and V
Figure 17., Reset, Power-Down
Waveform, for more details.
or Bus Write operations after
PEN
DDQ(IN)
, protects all blocks, pre-
PEN
IL
IH
, for at least t
with RP held at V
during power-up.
). The
Reset/Power-
IL
, during a
Program./
IH
, the
PLPH
13/60
PL-
IH
IL
.
.
.