Z8FMC04100 ZILOG [Zilog, Inc.], Z8FMC04100 Datasheet - Page 183

• Manufacturer Part Number: Z8FMC04100
• Description: Z8 Encore-R Motor Control Flash MCUs
• Manufacturer: ZILOG [Zilog, Inc.]

PS024604-1005
RESET
FIELD
ADDR
BITS
R/W
SPI Diagnostic State Register
SCKEN
7
SSIO—Slave Select I/O
0 = SS pin configured as an input.
1 = SS pin configured as an output (MASTER mode only).
SSV—Slave Select Value
If SSIO = 1 and SPI configured as a Master:
0 = SS pin driven Low (0).
1 = SS pin driven High (1).
This bit has no effect if SSIO = 0 or SPI configured as a Slave
The SPI Diagnostic State Register provides observability of internal state. It is a read-only
register used for SPI diagnostics. More detail about each bit follows the table.
SCKEN - Shift Clock Enable
0 = The internal Shift Clock Enable signal is deasserted
1 = The internal Shift Clock Enable signal is asserted (shift register is updates on next sys-
tem clock)
TCKEN - Transmit Clock Enable
0 = The internal Transmit Clock Enable signal is deasserted.
1 = The internal Transmit Clock Enable signal is asserted. When this is asserted the serial
data out is updated on the next system clock (MOSI or MISO).
000 = 8 bits
001 = 1 bit
010 = 2 bits
011 = 3 bits
100 = 4 bits
101 = 5 bits
110 = 6 bits
111 = 7 bits
TCKEN
Table 88. SPI Diagnostic State Register (SPIDST)
6
5
P R E L I M I N A R Y
4
F64H
00H
R
3
SPISTATE
Z8FMC16100 Series Flash MCU
2
SPI Diagnostic State Register
Product Specification
1
0
161