Z8FMC04100 ZILOG [Zilog, Inc.], Z8FMC04100 Datasheet - Page 50

• Manufacturer Part Number: Z8FMC04100
• Description: Z8 Encore-R Motor Control Flash MCUs
• Manufacturer: ZILOG [Zilog, Inc.]

28
Z8 Encore!
Product Specification
Reset and Stop-Mode Recovery
Operating Mode
Stop Mode
Stop-Mode Recovery
Stop-Mode Recovery Using Watch-Dog Timer Time-Out
Stop-Mode Recovery Using a GPIO Port Pin Transition
®
Motor Control Flash MCUs
STOP mode is entered by execution of a
Low-Power Modes
Mode Recovery, the device is held in reset for 66 cycles of the Internal Precision Oscilla-
tor. Stop-Mode Recovery only affects the contents of the
ter
in the Register File, including the Stack Pointer, Register Pointer, Flags, peripheral control
registers, and general-purpose RAM.
The eZ8 CPU fetches the Reset vector at Program Memory addresses
and loads that value into the Program Counter. Program execution begins at the Reset vec-
tor address. Following Stop-Mode Recovery, the STOP bit in the
Register
The text following provides more detailed information on each of the Stop-Mode Recov-
ery sources
If the Watch-Dog Timer times out during STOP mode, the device undergoes a Stop-Mode
Recovery sequence. In the
set to 1. If the Watch-Dog Timer is configured to generate a System Exception upon time-
out, the eZ8 CPU services the Watch-Dog Timer System Exception following the normal
Stop-Mode Recovery sequence.
Each of the GPIO port pins may be configured as a Stop-Mode Recovery input source. On
any GPIO pin enabled as a Stop-Mode Recovery source, a change in the input pin value
(from High to Low or from Low to High) initiates Stop-Mode Recovery. The GPIO Stop-
Mode Recovery signals are filtered to reject pulses less than 10ns (typical) in duration. In
the
and
Reset Status and Control
Table 8. Stop-Mode Recovery Sources and Resulting Action
Stop-Mode Recovery Source
Watch-Dog Timer time-out when
configured for Reset
Watch-Dog Timer time-out when
configured for System Exception
Data transition on any GPIO port pin
enabled as a Stop-Mode Recovery
source
Oscillator Control
is set to 1. Table 8 lists the Stop-Mode Recovery sources and resulting actions.
chapter on page 31 for detailed STOP mode information. During Stop-
Register. Stop-Mode Recovery does not affect any other values
Reset Status and Control
P R E L I M I N A R Y
Register, the STOP bit is set to 1.
STOP
instruction by the eZ8 CPU. Refer to the
Action
Stop-Mode Recovery
Stop-Mode Recovery followed by WDT
System Exception
Stop-Mode Recovery
Register, the WDT and STOP bits are
Reset Status and Control Regis-
Reset Status and Control
0002h
PS024604-1005
and
0003h