Z8FMC04100 ZILOG [Zilog, Inc.], Z8FMC04100 Datasheet - Page 196

• Manufacturer Part Number: Z8FMC04100
• Description: Z8 Encore-R Motor Control Flash MCUs
• Manufacturer: ZILOG [Zilog, Inc.]

174
Z8 Encore!
Product Specification
I2C Master/Slave Controller
S
Note:
Figure 30. Data Transfer Format—Master Read Transaction with a 7-Bit Address
®
Motor Control Flash MCUs
16. The I
17. The I
18. If more bytes remain to be sent, return to Step 14.
19. The software responds by asserting the
20. The I
21. The I
If the slave responds with a Not Acknowledge during the transfer, the I
asserts the
halts. The software terminates the transaction by setting either the
tion) or the
is flushed automatically.
Master Read Transaction with a 7-Bit Address
Figure 30 illustrates the data transfer format for a read operation to a 7-bit addressed slave.
The procedure for a master Read operation to a 7-bit addressed slave is as follows:
1. The software initializes the
2. The software writes the I
3. The software asserts the
4. If this operation is a single-byte transfer, the software asserts the NAK bit of the I
5. The I
6. The I
Slave Address
high period of SCL. The I
If the slave does not acknowledge, refer to the second paragraph of Step 11.
transmit interrupt asserts.
SLAVE mode with 7- or 10-bit addressing (the I
slave address types). The
addressed as a slave (but not for the remote slave). The software asserts the IEN bit in
the I
(which is set to 1).
Control Register so that after the first byte of data has been read by the I
a Not Acknowledge instruction is sent to the I
2
2
2
2
2
2
2
C Control Register.
C slave sends an Acknowledge by pulling the SDA signal Low during the next
C controller shifts the data out by the SDA signal. After the first bit is sent, the
C controller completes transmission of the data on the SDA signal.
C controller sends a
C controller sends a
C controller sends the address and Read bit out via the SDA signal.
NCKI
START
bit, sets the
bit (end this transaction, start a new one). The Transmit Data Register
R = 1
P R E L I M I N A R Y
START
2
ACKV
MODE
C Data Register with a 7-bit slave address, plus the Read bit
2
C controller sets the ACK bit in the I
STOP
START
MODE
A
bit, clears the
field selects the address width for this mode when
bit of the I
condition to the I
field in the I
condition.
Data
STOP
2
C Control Register.
ACK
bit of the I
2
2
C slave.
C Mode Register for MASTER/
2
C bus protocol allows the mixing of
bit in the I
2
C bus.
A
2
C Control Register.
2
Data
C State Register, and
STOP
2
C Status Register.
2
C controller
bit (end transac-
PS024604-1005
2
C controller,
A
P/S
2
C