Z8FMC04100 ZILOG [Zilog, Inc.], Z8FMC04100 Datasheet - Page 190

• Manufacturer Part Number: Z8FMC04100
• Description: Z8 Encore-R Motor Control Flash MCUs
• Manufacturer: ZILOG [Zilog, Inc.]

168
Z8 Encore!
Product Specification
I2C Master/Slave Controller
®
Motor Control Flash MCUs
Address (
on the unique slave address or the General Call/STARTBYTE address. The
automatically when the I2CISTAT Register is read.
If configured via the
ing, the most significant 7 bits of the first byte of the transaction are compared against the
SLA[6:0]
the first byte of the transaction is compared against {
ond byte is compared against
Arbitration Lost Interrupts
Arbitration Lost interrupts (
in MASTER mode and loses arbitration (outputs a 1 on SDA and receives a 0 on SDA).
The I
automatically when the I2CISTAT Register is read.
Stop/Restart Interrupts
A Stop/Restart event interrupt (
is in SLAVE mode and a
transaction. The
a
ter is expected to follow. This bit is cleared automatically when the I2CISTAT Register is
read. The STOP/RESTART interrupt only occurs on a selected (address match) slave.
Not Acknowledge Interrupts
Not Acknowledge interrupts (
Not Acknowledge is received or sent by the I
not set in the I
clears by setting the
the I
the Not Acknowledge interrupt occurs when a Not Acknowledge is received in response to
data sent. The
ter.
General Purpose Timer Interrupt from Baud Rate Generator
If the I
the I2CCTL Register = 1, an interrupt is generated when the baud rate generator (BRG)
counts down to 1. The baud rate generator reloads and continues counting, providing a
periodic interrupt. None of the bits in the I2CISTAT Register are set, allowing the BRG in
the I
abled.
STOP
2
2
2
C controller waits until it is cleared before performing any action. In SLAVE mode,
C controller to be used as a general-purpose timer when the I
C controller switches to SLAVE mode when this instance occurs. This bit clears
2
or
C controller is disabled (
GCA
RESTART
bits of the Slave Address Register. If configured for 10-bit slave addressing,
) bit of the I2CISTAT Register indicates whether the address match occurred
2
NCKI
C Control Register. In MASTER mode, the Not Acknowledge interrupt
RSTR
START
bit clears in SLAVE mode when software reads the I2CISTAT Regis-
condition. When a restart occurs, a new transaction by the same mas-
MODE[1:0]
bit in the I2C State Register indicates whether the bit was set due to
STOP
P R E L I M I N A R Y
ARBLST
or
NCKI
SLA[7:0]
STOP
or
SPRS
IEN
RESTART
field of the I
bit = 1 in I2CISTAT) occur in MASTER mode when a
bit = 1 in I2CISTAT) occur when the I
bit. When this interrupt occurs in MASTER mode,
bit in the I2CCTL Register = 0) and the
bit = 1 in I2CISTAT) occurs when the I
.
condition is received, indicating the end of the
2
C controller and the
2
C Mode Register for 7-bit slave address-
11110
,
SLA[9:8]
2
START
C controller is dis-
,R/W} and the sec-
2
or
C controller is
PS024604-1005
SAM
2
STOP
C controller
BIRQ
bit clears
bit is
bit in