Z8FMC04100 ZILOG [Zilog, Inc.], Z8FMC04100 Datasheet - Page 81
Z8FMC04100
Manufacturer Part Number
Z8FMC04100
Description
Z8 Encore-R Motor Control Flash MCUs
Manufacturer
ZILOG [Zilog, Inc.]
Datasheet
1.Z8FMC04100.pdf
(402 pages)
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PS024604-1005
RESET
FIELD
ADDR
BITS
R/W
IRQ1 Enable High and Low Bit Registers
PWMENL
R/W
7
0
Table 34. IRQ0 Enable Low Bit Register (IRQ0ENL)
T0ENH—Timer 1 Interrupt Request Enable High Bit
U0RENH—UART 0 Receive Interrupt Request Enable High Bit
U0TENH—UART 0 Transmit Interrupt Request Enable High Bit
SPIENH—SPI Interrupt Request Enable High Bit
PWMENL—Pulse-Width Modulator Interrupt Request Enable Low Bit
FLTENL—Fault Interrupt Request Enable Low Bit
ADCENL—ADC Interrupt Request Enable Low Bit
CMPENL—Comparator Interrupt Request Enable Low Bit
T0ENL—Timer 0 Interrupt Request Enable Low Bit
U0RENL—UART 0 Receive Interrupt Request Enable Low Bit
U0TENL—UART 0 Transmit Interrupt Request Enable Low Bit
SPIENL—SPI Interrupt Request Enable Low Bit
The IRQ1 Enable High and Low Bit registers, shown in Tables 36 and 37, form a priority
encoded enabling for interrupts in the Interrupt Request 1 register. Priority is generated by
setting bits in each register. Table 35 describes the priority control for IRQ1.
Table 35. IRQ1 Enable and Priority Encoding
x indicates the register bits from 0 through 7.
IRQ1ENH[x] IRQ1ENL[x] Priority
0
0
1
1
FLTENL
R/W
6
0
ADCENL
0
1
0
1
R/W
5
0
P R E L I M I N A R Y
Disabled
Level 1
Level 2
Level 3
CMPENL
R/W
4
0
FC2H
T0ENL
R/W
Description
Disabled
Low
Nominal
High
3
0
Z8FMC16100 Series Flash MCU
IRQ1 Enable High and Low Bit Registers
U0RENL
R/W
2
0
Product Specification
U0TENL
R/W
1
0
SPIENL
R/W
0
0
59
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