Z8FMC04100 ZILOG [Zilog, Inc.], Z8FMC04100 Datasheet - Page 209

• Manufacturer Part Number: Z8FMC04100
• Description: Z8 Encore-R Motor Control Flash MCUs
• Manufacturer: ZILOG [Zilog, Inc.]

PS024604-1005
Note:
I
2
C Baud Rate High and Low Byte Registers
STOP—Send Stop Condition
When set, this bit causes the I
STOP condition after the byte in the I
a byte has been received in a receive operation. When set, this bit is reset by the I
troller after a STOP condition has been sent or by deasserting the
cannot be cleared to 0 by writing to the register.
If STOP is set while a slave mode transaction is underway, the STOP bit will be cleared by
hardware.
BIRQ—Baud Rate Generator Interrupt Request
This bit is ignored when the I
Controller is disabled (
ing an interrupt to occur every time the baud rate generator counts down to one. The baud
rate generator runs continuously in this mode, generating periodic interrupts.
TXI—Enable TDRE interrupts
This bit enables interrupts when the I
NAK—Send NAK
Setting this bit sends a Not Acknowledge condition after the next byte of data has been
received. It is automatically deasserted after the Not Acknowledge is sent or the IEN bit is
cleared. If this bit is 1, it cannot be cleared to 0 by writing to the register.
FLUSH—Flush Data
Setting this bit clears the I
ing of the I
has been written to the I
FILTEN—I
Setting this bit enables low-pass digital filters on the SDA and SCL input signals. This
function provides the spike suppression filter required in I2C Fast Mode. These filters
reject any input pulse with periods less than a full system clock cycle. The filters introduce
a 3-system clock cycle latency on the inputs.
The I
form a 16-bit reload value,
is calculated using the following equation.
If
I
2
C Baud Rate (bits/s) =
BRG
2
C Baud Rate High and Low Byte registers, shown in Tables 95 and 96, combine to
=
0000h
2
2
C Data register when an NAK condition is received after the next data byte
C Signal Filter Enable
, use
10000h
IEN
2
C Data register. Reading this bit always returns 0.
2
C Data register and sets the
BRG
= 0) the baud rate generator is used as an additional timer caus-
P R E L I M I N A R Y
System Clock Frequency (Hz)
2
2
in the equation):
C Controller is enabled. If this bit is set = 1 when the I
C Controller (when configured as the Master) to send the
[15:0], for the I
4 x BRG[15:0]
2
2
C Data register is empty.
C Shift register has completed transmission or after
2
C Baud Rate Generator. The I
I2C Baud Rate High and Low Byte Registers
Z8FMC16100 Series Flash MCU
TDRE
bit to 1. This bit allows flush-
Product Specification
IEN
bit. If this bit is 1, it
2
C baud rate
2
C Con-
2
C
187