Z8FMC04100 ZILOG [Zilog, Inc.], Z8FMC04100 Datasheet - Page 95
Z8FMC04100
Manufacturer Part Number
Z8FMC04100
Description
Z8 Encore-R Motor Control Flash MCUs
Manufacturer
ZILOG [Zilog, Inc.]
Datasheet
1.Z8FMC04100.pdf
(402 pages)
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PS024604-1005
Minimum PWM Pulse Width Filter
Synchronization of PWM and Analog-to-Digital Converter
counter directly counts system clock cycles and is unaffected by PWM prescaler settings.
The width of this deadband is attributed to the number of system clock cycles specified in
the PWM Deadband Register (PWMDB). The minimum deadband duration is one system
clock, and the maximum duration is 255 system clocks. During the deadband period, both
PWM outputs of a complementary pair are deasserted. The generation of deadband time
does not alter the PWM period; instead, the deadband time is subtracted from the active
time of the PWM outputs.
PWM output.
The PWM modulator is capable of producing pulses as narrow as a single system clock
cycle in width. Because the response time of external drive circuits may be slower than the
period of a system clock, a filter is implemented to enforce a minimum-width pulse on the
PWM output pins. All output pulses, whether High or Low, must be at least the minimum
number of PWM clock cycles (see the
mation) in width as specified in the PWM Minimum Pulse Width Filter (PWMMPF) Reg-
ister. If the expected pulse width is less than the threshold, the associated PWM output
does not change state until the duty cycle value has changed sufficiently to allow pulse
generation of an acceptable width. The minimum pulse width filter also accounts for the
duty cycle variation caused by the deadband insertion. The PWM output pulse is filtered
even if the programmed duty cycle is greater than the threshold, but the pulse width
decrease because of deadband insertion causes the pulse to be too narrow. The pulse width
filter value is calculated as:
where
The PWM Minimum Pulse Width Filter Register can only be written when the
cleared. Values written to this register when
The analog-to-digital converter (ADC) on the Z8FMC16100 Series Flash MCU can be
synchronized with the PWM period. Enabling the PWM ADC trigger causes the PWM to
generate an ADC conversion signal at the end of each PWM period. Additionally, in cen-
ter-aligned mode, the PWM will generate a trigger at the center of the period. Setting the
ADCTRIG bit in the PWM Control 0 Register (PWMCTL0) enables ADC synchroniza-
tion.
roundup(PWMMPF) =
T
MINPULSEOUT
is the shortest allowed pulse width on the PWM outputs, in seconds.
Figures 8 and 9
T
P R E L I M I N A R Y
SYSTEMCLOCK
T
MINPULSEOUT
PWM Prescaler
show the effect of deadband insertion on the
x PWM
PWEN
PRESCALER
is set will be ignored.
section on page 70 for more infor-
Minimum PWM Pulse Width Filter
Product Specification
PWEN
bit is
73
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