AM29BDS320G SPANSION [SPANSION], AM29BDS320G Datasheet - Page 14

• Manufacturer Part Number: AM29BDS320G
• Description: 32 Megabit (2 M x 16-Bit), 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
• Manufacturer: SPANSION [SPANSION]

Device Bus Operations
Legend: L = Logic 0, H = Logic 1, X = Don’t Care, S = Stable Logic 0 or 1 but no transitions.
Note: Default active edge of CLK is the rising edge.
12
Operation
Asynchronous Read - Addresses Latched
Asynchronous Read - Addresses Steady State
Asynchronous Write
Synchronous Write
Standby (CE#)
Hardware Reset
Burst Read Operations
Load Starting Burst Address
Advance Burst to next address with
appropriate Data presented on the Data Bus
Terminate current Burst read cycle
Terminate current Burst read cycle via RESET#
Terminate current Burst read cycle and start
new Burst read cycle
Enhanced VersatileIO™ (V
Requirements for Asynchronous Read
Operation (Non-Burst)
This section describes the requirements and use of the device bus operations,
which are initiated through the internal command register. The command register
itself does not occupy any addressable memory location. The register is com-
posed of latches that store the commands, along with the address and data
information needed to execute the command. The contents of the register serve
as inputs to the internal state machine. The state machine outputs dictate the
function of the device. Table 1 lists the device bus operations, the inputs and con-
trol levels they require, and the resulting output. The following subsections
describe each of these operations in further detail.
The Enhanced VersatileIO (V
levels that the device generates at its data outputs and the voltages tolerated at
its data and address inputs to the same voltage level that is asserted on the V
pin. The device is available with either 1.65–1.95 or 2.7–3.15 V
device to operate in 1.8 V or 3 V system environments as required.
For example, a V
and receiving signals to and from other 3 V devices on the same bus.
To read data from the memory array, the system must first assert a valid address
on A20–A0, while driving AVD# and CE# to V
rising edge of AVD# latches the address. The data will appear on DQ15–DQ0.
IO
of 2.7 – 3.15 volts allows for I/O at the 3 volt level, driving
Table 1. Device Bus Operations
IO
) Control
IO
CE#
H
X
H
X
) control allows the host system to set the voltage
L
L
L
L
L
L
L
Am29BDS320G
P r e l i m i n a r y
OE#
H
H
X
X
X
L
L
X
L
X
X
WE#
IL
H
H
X
X
H
H
H
H
H
L
L
. WE# should remain at V
Addr In
Addr In
Addr In
Addr In
HIGH Z
HIGH Z
Addr In
HIGH Z
HIGH Z
HIGH Z
HIGH Z
A20–0
Data Out
DQ15–0
HIGH Z
HIGH Z
HIGH Z
HIGH Z
IO
Burst
I/O
I/O
I/O
I/O
I/O
. This allows the
X
RESET#
IH
H
H
H
H
H
H
H
H
H
. The
L
L
IO
27243B1 October 1, 2003
Note) AVD#
(See
CLK
X
X
X
X
X
L
H
L
L
X
X
X
X