AM29BDS320G SPANSION [SPANSION], AM29BDS320G Datasheet - Page 34

• Manufacturer Part Number: AM29BDS320G
• Description: 32 Megabit (2 M x 16-Bit), 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
• Manufacturer: SPANSION [SPANSION]

32
Chip Erase Command Sequence
the same manner. This mode dispenses with the initial two unlock cycles required
in the standard program command sequence, resulting in faster total program-
ming time. The host system may also initiate the chip erase and sector erase
sequences in the unlock bypass mode. The erase command sequences are four
cycles in length instead of six cycles.
page 36
During the unlock bypass mode, only the Unlock Bypass Program, Unlock Bypass
Sector Erase, Unlock Bypass Chip Erase, and Unlock Bypass Reset commands are
valid. To exit the unlock bypass mode, the system must issue the two-cycle un-
lock bypass reset command sequence. The first cycle must contain the bank
address and the data 90h. The second cycle need only contain the data 00h. The
bank then returns to the read mode.
The device offers accelerated program operations through the ACC input. When
the system asserts V
Bypass mode. The system may then write the two-cycle Unlock Bypass program
command sequence. The device uses the higher voltage on the ACC input to ac-
celerate the operation.
Figure 2
Program Operations table in the AC Characteristics section for parameters, and
Figure 21, “Asynchronous Program Operation Timings,” on page 58
diagrams.
Chip erase is a six bus cycle operation. The chip erase command sequence is ini-
tiated by writing two unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the chip erase command,
which in turn invokes the Embedded Erase algorithm. The device does not require
shows the requirements for the unlock bypass command sequences.
illustrates the algorithm for the program operation. Refer to the Erase/
ID
No
on this input, the device automatically enters the Unlock
Figure 2. Erase Operation
Command Sequence
Erasure Completed
from System
Write Erase
Data = FFh?
Data Poll
Am29BDS320G
START
P r e l i m i n a r y
Yes
Table 14, “Command Definitions,” on
Embedded
Erase
algorithm
in progress
for timing
27243B1 October 1, 2003