AM29BDS320G SPANSION [SPANSION], AM29BDS320G Datasheet - Page 29

• Manufacturer Part Number: AM29BDS320G
• Description: 32 Megabit (2 M x 16-Bit), 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
• Manufacturer: SPANSION [SPANSION]

October 1, 2003 27243B1
Notes:
1. Upon power-up or hardware reset, the default setting is seven wait states.
2. RDY will default to being active with data when the Wait State Setting is set to a
3. Assumes even address.
It is recommended that the wait state command sequence be written, even if the
default wait state value is desired, to ensure the device is set as expected. A
hardware reset will set the wait state to the default setting.
Reduced Wait-State Handshaking Option
If the device is equipped with the reduced wait-state handshaking option, the
host system should set address bits A14–A12 to 010 for a clock frequency of 40
MHz or to 011 for a clock frequency of 54 MHz for the system/device to execute
at maximum speed.
Table
conditions.
Note: In the 8-, 16- and 32-word burst read modes, the address pointer does not
cross 64-word boundaries (3Fh, and addresses offset from 3Fh by a multiple of 64).
The autoselect function allows the host system to determine whether the flash
device is enabled for reduced wait-state handshaking. See the “Autoselect Com-
mand Sequence” section for more information.
6–11 MHz
12–23 MHz
24–33 MHz
34–40 MHz
40–47 MHz
48–54 MHz
Frequency
total initial access cycle of 2.
System
Range
9
A14
0
0
0
0
1
1
describes the typical number of clock cycles (wait states) for various
Even
Initial
Addr.
Table 8. Programmable Wait State Settings
Table 9. Initial Access Cycles vs. Frequency
P r e l i m i n a r y
2
2
3
4
4
5
A13
0
0
1
1
0
0
Odd
Initial
Addr.
2
3
4
5
5
6
Am29BDS320G
Even
Initial
Addr.
with
Boundary
A12
0
1
0
1
0
1
3
4
5
6
6
7
Odd Initial
Addr.
with
Boundary
Total Initial Access Cycles
4
5
6
7
7
8
2
3
4
5
6
7
Device Speed
40 MHz
54 MHz
Rating
27