HY27US08561M HYNIX [Hynix Semiconductor], HY27US08561M Datasheet
HY27US08561M
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HY27US08561M Summary of contents
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Document Title 256Mbit (32Mx8bit / 16Mx16bit) NAND Flash Memory Revision History No. 0.0 Initial Draft 0.1 Renewal Product Group 0.2 Append 1.8V Operation Product to Data sheet Insert Spare Enable function for GND Pin(# case of Reading or ...
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... TSOP1 ( 1.2 mm) - HY27US(08/16)561M-T (Lead) - HY27US(08/16)561M-TP (Lead Free) - HY27US08561M-V(P) : 48-Pin WSOP1 ( 0.7 mm) - HY27US08561M-V (Lead) - HY27US08561M-VP (Lead Free) - HY27(U/S)S(08/16)561M-F(P) : 63-Ball FBGA (9 1.0 mm) - HY27US(08/16)561M-F (Lead) - HY27US(08/16)561M-FP (Lead Free) - HY27SS(08/16)561M-F (Lead) - HY27SS(08/16)561M-FP (Lead Free) ...
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DESCRIPTION The HYNIX HY27(U/S)SXX561M series is a family of non-volatile Flash memories that uses NAND cell technology. The devices operate 3.3V and 1.8V voltage supply. The size of a Page is either 528 Bytes (512 + 16 spare) or 264 ...
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Vcc GND CE RE NAND Flash WE ALE CLE WP Vss Figure 1: Logic Diagram Address Register/Counter ALE CLE Command WE Interface CE Logic WP RE Command Register Rev 0.7 / Oct. 2004 256Mbit (32Mx8bit / 16Mx16bit) NAND Flash I/O ...
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GND GND GND NAND Flash ...
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Figure 5. 63-FBGA Contactions, x8 Device (Top view through package ...
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MEMORY ARRAY ORGANIZATION The memory array is made up of NAND structures where 16 cells are connected in series. The memory array is organized in blocks where each block contains 32 pages. The array is split into two areas, the ...
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SIGNAL DESCRIPTIONS See Figure 1, Logic Diagram and Table 1, Signal Names, for a brief overview of the signals connected to this device. Inputs/Outputs (I/O -I Input/Outputs are used to input the selected address, ...
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Ready/Busy (RB) The Ready/Busy output, RB open-drain output that can be used to identify if the Program/ Erase/ Read (PER) Controller is currently active. When Ready/Busy is Low read, program or erase operation is in ...
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Data Input Data Input bus operations are used to input the data to be programmed. Data is accepted only when Chip Enable is Low, Address Latch Enable is Low, Command Latch Enable is Low and Read Enable is High. The ...
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Table 2. Bus Operation BUS Operation CE Command Input V IL Address Input V IL Data Input V IL Data Output V IL Write Protect X V Standby IH Note : (1) Only for x16 devices. (2) WP must be ...
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COMMAND SET All bus write operations to the device are interpreted by the Command Interface. The Commands are input on I/O O and are latched on the rising edge of Write Enable when the Command Latch Enable signal is high. ...
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However, the Read B command is effective for only one operation, once an operation has been executed in Area B the pointer returns automatically to Area A. The pointer operations can also be used before a ...
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Read Memory Array Each operation to read the memory area starts with a pointer operation as shown in the Pointer Operations section. Once the area (main or spare) has been selected using the Read A, Read B or Read C ...
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CLE CE WE ALE RE RB 00h/ I/O 01h/ 50h Command Code Note less than 10ns, t ELWL Read A Command, x8 Devices Area A (1st half Page) A9-A24(1) A0-A7 Read B Command, x8 Devices Area ...
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Busy time) RB 00h/ I/O Address Inputs 01h/50h Command Code Read A Command, x8 Devices Area B Area A (2nd half (1st half Page) Page) Block Note : GND input=L, 00h Command Read B Command, x8 Devices Area B ...
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Page Program The Page Program operation is the standard operation to program data to the memory array. The main area of the memory array is programmed by page, however partial page programming is allowed where any number of bytes (1 ...
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Copy Back Program The Copy Back Program operation is used to copy the data stored in one page and reprogram it in another page. The Copy Back Program operation does not require external memory and so the operation is faster ...
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RB Block Address I/O 60h Inputs Block Erase Setup Code Reset The Reset command is used to reset the Command Interface and Status Register. If the Reset command is issued dur- ing any operation, the operation will be aborted. If ...
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P/E/R Controller Bit (SR5) The Program/Erase/Read Controller bit indicates whether the P/E/R Controller is active or inactive. When the P/E/R Controller bit is set to '0', the P/E/R Controller is active (device is busy); when the bit is set to ...
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... Bus Write cycle to issue the Read Electronic Signature command (90h) 2. then subsequent Bus Read operations will read the Manufacturer Code and the Device Code until another command is issued. Refer to Table, Read Electronic Signature for information on the addresses. Part Number HY27US08561M HY27SS08561M HY27US16561M HY27SS16561M Automatic Page 0 Read at Power-Up Automatic Page 0 Read at Power- option available on all devices belonging to the NAND Flash 528 Byte/264 Word Page family ...
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Automatic Page 0 Read Description. At powerup, once the supply voltage has reached the threshold level, V state and the internal NAND device functions (reading, writing, erasing) are enabled. The device then automatically switches to read mode where ...
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Vccth(1) Vcc WE CE ALE CLE tBLBH1 (Read Busy time) RB Busy I/O Note: (1 equal to 2.0V for 3.3V and to 1.5V for 1.8V Power Supply devices. CCth Figure 19. Automatic Page 0 Read at power-up (Sequential ...
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Block Address= Table 8: Valid Block Symbol Valid Block VB PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES The Program and Erase times and the number of Program/ Erase cycles per block are shown in Table 9. Rev ...
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Table 9: Program, Erase Time and Program Erase Endurance Cycles Parameters Page Program Time Block Erase Time Program/Erase Cycles (per block) Data Retention MAXIMUM RATING Stressing the device above the ratings listed in Table 10, Absolute Maximum Ratings, may cause ...
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Table 11: Operating and AC Measurement Conditions Parameter Supply Voltage ( Ambient Temperature (T A Load Capacitance ( TTL GATE and C L Input Pulses Voltages Input and Output Timing Ref. Voltages Input Rise and Fall ...
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Table 13: DC Characteristics, 3.3V Device and 1.8V Device Symbol Parameter Sequentia I CC1 Read Operating I Current Program CC2 I Erase CC3 I Stand-by Current (TTL) CC4 Stand-By Current I CC5 (CMOS) I Input Leakage Current LI I Output ...
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Table 14: AC Characteristics for Command, Address, Data Input (3.3V Device and 1.8V Device) Alt. Symbol Symbol t Address Latch Low to Write Enable Low ALLWL t ALS t Address Latch Hith to Write Enable Low ALHWL Command Latch High ...
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Table 15: AC Characteristics for Operation (3.3V Device and 1.8V Device) Alt. Sym- Sym- bol bol t t ALLRL1 AR1 Address Latch Low to Read En- able Low t t ALLRL2 AR2 t t Ready/Busy High to Read Enable Low ...
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Alt. Sym- Sym- bol bol t REA t Read Enable Low to Output Valid RLQV t READID t t Write Enable High to Ready/Busy High WHBH Write Enable High to Ready/Busy Low WHBL Write ...
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CLE tELWL (CE Setup time) CE tWLWH WE tALHWL (ALE Setup time) (AL Hold time) ALE tDVWH (Data Setup time) I/O CLE CE tALLWL (ALE Setup time) ALE tWLWH WE tDVWH (Data Setup time) I/O Rev 0.7 / Oct. 2004 ...
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CE (RE High Holdtime) RE tRLQV (RE Accesstime) I/O tBHRL RB Figure 24. Sequential Data Output after Read AC Waveforms Note:1. CLE = Low, ALE = Low High. CLE tCLHWL CE tELWL WE RE tDVWH (Data Setup time) ...
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CLE CE WE ALE RE I/O 90h Read Electronic Signature Command Figure 26. Read Electronic Signature AC Waveform Note: Refer to table(To see Page 22) for the values of the manufacture and device codes. CLE CE tWHWL WE ALE RE ...
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Note: 1. A0-A7 is the address in the Spare Memory area, where A0-A3 are valid and A4-A7 are don't care. 2. Only address cycle 4 is required. CLE CE WE ALE RE I/O 50h RB Command Code Figure 28. Read ...
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CLE CE tWLWL (Write Cycle time) WE ALE RE Add. N I/O 80h cycle 1 RB Page Program Setup Code Rev 0.7 / Oct. 2004 256Mbit (32Mx8bit / 16Mx16bit) NAND Flash tWLWL Add. N Add cycle 2 cycle ...
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CLE CE tWLWL (Write Cycle time) WE ALE RE Add. N I/O 60h cycle 1 RB Block Erase Setup Command Block Address Input WE ALE CLE RE I/O FFh RB Rev 0.7 / Oct. 2004 256Mbit (32Mx8bit / 16Mx16bit) NAND ...
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System Interface Using CE don’t care To simplify system interface, CE may be deasserted during data loading or sequential data-reading as shown below. So possible to connect NAND Flash to a microprocessor. The only function that was removed ...
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Ready/Busy Signal Electrical Characteristics Figures 32, 33 and 34 show the electrical characteristics for the Ready/Busy signal. The value required for the resistor R can be calculated using the following equation: P where I is the sum of the input ...
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Figure 35. Resistor Value Waveform Timings for Ready/Busy Signal Rev 0.7 / Oct. 2004 256Mbit (32Mx8bit / 16Mx16bit) NAND Flash Vcc=1.8, CL=30pF 1.7 0. 1.7 1 ...
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Figure 36. 48-TSOP1 - 48-lead Plastic Thin Small Outline 20mm, Package Outline Table 16: 48-TSOP1 - 48-lead Plastic Thin Small Outline 20mm, Package Mechanical Data Symbol ...
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Figure 37. 48-WSOP1 - 48-lead Plastic Thin Small Outline 17mm, Package Outline Table 17: 48-WSOP1- 48-lead Plastic Very Very Thin Small Outline, 12x17mm, Package Mechanical Data Symbol ...
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Figure 38. 63-FBGA - 9.0 x 11, 6x8 ball array 0.8mm pitch, Pakage Outline Note: Drawing is not to scale. Table 18: 63-FBGA - 9.0 x 11, 6x8 ball array 0.8mm pitch, Pakage Outline Mechanical Data Symbol ...
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MARKING INFORMATION - Packag TSOP1 / WSOP - hynix - KOR - HY27xSxx121mTxB HY: HYNIX 27: NAND Flash x: Power Supply S: Classification xx: Bit Organization 56: Density 1: Mode M: Version x: Package Type x: Package Material x: Operating ...
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MARKING INFORMATION - Packag FBGA - HY27xSxx121mTxB HY: HYNIX x: Power Supply S: Classification xx: Bit Organization 56: Density 1: Mode M: Version x: Package Material x: Operating Temperature x: Bad Block - Y: Year (ex: 4=year 2004, 05= year ...