HY27US08561M HYNIX [Hynix Semiconductor], HY27US08561M Datasheet - Page 12

• Manufacturer Part Number: HY27US08561M
• Description: 256Mbit (32Mx8bit / 16Mx16bit) NAND Flash
• Manufacturer: HYNIX [Hynix Semiconductor]

COMMAND SET
All bus write operations to the device are interpreted by the Command Interface. The Commands are input on I/O
O
tions are selected by writing specific commands to the Command Register. The two-step command sequences for pro-
gram and erase operations are imposed to maximize data security.
The Commands are summarized in Table 5, Commands.
Table 5: Command Set
Note: (1). Any undefined command sequence will be ignored by the device.
DEVICE OPERATIONS
Pointer Operations
As the NAND Flash memories contain two different areas for x16 devices and three different areas for x8 devices (see
Figure 8) the read command codes (00h, 01h, 50h) are used to act as pointers to the different areas of the memory
array (they select the most significant column address).
The Read A and Read B commands act as pointers to the main memory area. Their use depends on the bus width of
the device.
to 255.
to 255, and the Read B command (01h) sets the pointer to Area B (the second half of the main area) that is Bytes 256
to 511.
In both the x8 and x16 devices the Read C command (50h), acts as a pointer to Area C (the spare memory area) that
is Bytes 512 to 527 or Words 256 to 263.
Once the Read A and Read C commands have been issued the pointer remains in the respective areas until another
Rev 0.7 / Oct. 2004
- In x16 devices the Read A command (00h) sets the pointer to Area A (the whole of the main area) that is Words 0
- In x8 devices the Read A command (00h) sets the pointer to Area A (the first half of the main area) that is Bytes 0
7
READ A
READ B
READ C
READ ELECTRINIC SIGNATURE
READ STATUS REGISTER
PAGE PROGRAM
COPY BACK PROGRAM
BLOCK ERASE
RESET
and are latched on the rising edge of Write Enable when the Command Latch Enable signal is high. Device opera-
(2). The 50h command is valid only when GND(Pin#6) is Low.
(3). Bus Write Operation(1
FUNCTION
st
, 2
nd
and 3
1st CYCLE
01h
50h
00h
90h
70h
80h
00h
60h
FFh
rd
(1)
(2)
Cycle) : The bus cycles are only shown for issuing the codes. The cycles required to
256Mbit (32Mx8bit / 16Mx16bit) NAND Flash
input the addresses or input/output data are not shown.
2nd CYCLE
D0h
10h
8Ah
-
-
-
-
-
-
3rd CYCLE
10h
-
-
-
-
-
-
-
-
HY27US(08/16)561M Series
HY27SS(08/16)561M Series
Command accepted during busy
Yes
Yes
0
-I/
12