HY27US08561M HYNIX [Hynix Semiconductor], HY27US08561M Datasheet - Page 11

• Manufacturer Part Number: HY27US08561M
• Description: 256Mbit (32Mx8bit / 16Mx16bit) NAND Flash
• Manufacturer: HYNIX [Hynix Semiconductor]

Table 2. Bus Operation
Note : (1) Only for x16 devices.
Table 3: Address Insertion, x8 Devices
Note: (1). A8 is set Low or High by the 00h or 01h Command, see Pointer Operations section.
Table4: Address Insertion, x16 Devices
Note: (1). L must be set ''LOW''.
Rev 0.7 / Oct. 2004
Bus Cycle
Command Input
Address Input
Data Input
Data Output
Write Protect
Standby
1st Cycle
2nd Cycle
3rd Cycle
1st Cycle
2nd Cycle
3rd Cycle
Bus Cycle
BUS Operation
(2). Any additional input cycles will be ignored with tALS > 0ns.
(2). A8 is Don't Care in x16 devices.
(3). Any additional input cycles will be ignored with tALS > 0ns.
(4). A1 is the Least Significant Address for x16 devices.
(5). The 01h Command is not used in x16 devices.
(2) WP must be V
I/O
L
L
L
8
(1)
(1)
(1)
-IO
I/O
A16
A24
A7
IH
15
7
when issing a program or erase command.
V
CE
V
V
V
V
X
IH
IL
IL
IL
IL
I/O
A16
A24
A7
7
I/O
A15
A23
A6
ALE
V
V
V
V
X
X
6
IH
IL
IL
IL
I/O
A15
A23
A6
6
CLE
V
V
V
V
I/O
X
X
IH
IL
IL
IL
A14
A22
A5
256Mbit (32Mx8bit / 16Mx16bit) NAND Flash
5
I/O
A14
A22
Falling
A5
V
V
V
RE
X
X
5
IH
IH
IH
I/O
A13
A21
A4
4
Rising
Rising
Rising
I/O
WE
A13
A21
V
A4
X
X
IH
4
I/O
A12
A20
A3
HY27US(08/16)561M Series
HY27SS(08/16)561M Series
WP
X
V
X
X
X
X
(2)
3
I/O
IL
A12
A20
A3
3
I/O
I/O
Data Output
A11
A19
Data Input
Command
A2
Address
I/O
A11
A19
0
2
A2
X
X
- I/O
2
7
I/O
A10
A18
A1
I/O
A10
A18
A1
1
I/O
1
Data Output
Data Input
8
- I/O
X
X
X
X
I/O
I/O
A17
A17
A0
A9
A0
A9
15
0
0
(1)
11