AM29LV2562M AMD [Advanced Micro Devices], AM29LV2562M Datasheet - Page 41

• Manufacturer Part Number: AM29LV2562M
• Manufacturer: AMD [Advanced Micro Devices]

Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Tables
11
chip erase command sequence.
December 16, 2005
No
Figure 6. Program Suspend/Program Resume
show the address and data requirements for the
Sequence in Progress
Program Operation
Write address/data
Write address/data
Program Suspend
or Write-to-Buffer
operation prior to
Device reverts to
Read data as
Wait 15 µs
XXXh/B0h
XXXh/30h
reading?
required
Done
Yes
Write Program Suspend
Command Sequence
Command is also valid for
Erase-suspended-program
operations
Autoselect and SecSi Sector
read operations are also allowed
Data cannot be read from erase- or
program-suspended sectors
Write Program Resume
Command Sequence
D A T A S H E E T
10
Am29LV2562M
and
When the Embedded Erase algorithm is complete, the
device returns to the read mode and addresses are no
longer latched. The system can determine the status
of the erase operation by using DQ7 and DQ15, DQ6
and DQ14, or DQ2 and DQ10. Refer to the
eration Status
bits.
Any commands written during the chip erase operation
are ignored. However, note that a hardware reset im-
mediately terminates the erase operation. If that oc-
curs, the chip erase command sequence should be
reinitiated once the device has returned to reading
array data, to ensure data integrity.Note that the SecSi
Sector, autoselect, and CFI functions are unavailable
when an erase operation in is progress.
Figure illustrates the algorithm for the erase opera-
tion. Refer to the
bles in the AC Characteristics section for parameters,
and Figure 18 section for timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two ad-
ditional unlock cycles are written, and are then fol-
lowed by the address of the sector to be erased, and
the sector erase command. Table 11 shows the ad-
dress and data requirements for the sector erase com-
mand sequence.
The device does not require the system to preprogram
prior to erase. The Embedded Erase algorithm auto-
matically programs and verifies the entire memory for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
After the command sequence is written, a sector erase
time-out of 50 µs occurs. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time
between these additional cycles must be less than 50
µs, otherwise erasure may begin. Any sector erase ad-
dress and command following the exceeded time-out
may or may not be accepted. It is recommended that
processor interrupts be disabled during this time to en-
sure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is
written. Any command other than Sector Erase or
Erase Suspend during the time-out period resets
the device to the read mode. The system must re-
write the command sequence and any additional ad-
dresses and commands. Note that the SecSi Sector,
autoselect, and CFI functions are unavailable when an
erase operation in is progress.
section for information on these status
Erase and Program Operations
Write Op-
39
ta-