AM29LV2562M AMD [Advanced Micro Devices], AM29LV2562M Datasheet - Page 47

• Manufacturer Part Number: AM29LV2562M
• Manufacturer: AMD [Advanced Micro Devices]

DQ2 and DQ10: Toggle Bits II
The “Toggle Bits II” on DQ2 and DQ10, when used
with DQ6 and DQ14, indicate whether a particular
sector is actively erasing (that is, the Embedded Erase
algorithm is in progress), or whether that sector is
erase-suspended. Toggle Bits II are valid after the ris-
ing edge of the final WE# pulse in the command se-
quence.
DQ2 and DQ10 toggle when the system reads at ad-
dresses within those sectors that have been selected
for erasure. (The system may use either OE# or CE#
to control the read cycles.) But DQ2 and DQ10 cannot
distinguish whether the sector is actively erasing or is
erase-suspended. DQ6 and DQ14, by comparison, in-
dicate whether the device is actively erasing, or is in
Erase Suspend, but cannot distinguish which sectors
are selected for erasure. Thus, both status bits are re-
quired for sector and mode information. Refer to Table
12 to compare outputs for DQ2 and DQ10 and DQ6
and DQ14.
Figure 8 shows the toggle bit algorithm in flowchart
form, and the section “DQ2 and DQ10: Toggle Bits II”
explains the algor ithm. See also the
Ready/Busy#
bit timing diagram. Figure 21 shows the differences
between DQ2 and DQ10 and DQ6 and DQ14 in
graphical form.
Reading Toggle Bits DQ6 and DQ14/DQ2
and DQ10
Refer to Figure 8 for the following discussion. When-
ever the system initially begins reading toggle bits sta-
tus, it must read DQ15–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically,
the system would note and store the value of the tog-
gle bit after the first read. After the second read, the
system would compare the new value of the toggle bit
with the first. If the toggle bits are not toggling, the de-
vice has completed the program or erase operation.
The system can read array data on DQ15–DQ0 on the
following read cycle.
However, if after the initial two read cycles, the system
determines that one of the toggle bits are still toggling,
the system also should note whether the value of DQ5
and DQ13 is high (see the section on DQ5 and DQ13).
If it is, the system should then determine again
whether the toggle bit is toggling, since the toggle bit
may have stopped toggling just as DQ5 and/or DQ13
went high. If the toggle bits are no longer toggling, the
device has successfully completed the program or
erase operation. If it is still toggling, the device did not
completed the operation successfully, and the system
must write the reset command to return to reading
array data.
December 16, 2005
subsection. Figure 20 shows the toggle
RY/BY#:
D A T A S H E E T
Am29LV2562M
The remaining scenario is that the system initially de-
termines that the toggle bit is toggling and DQ5 and/or
DQ13 has not gone high. The system may continue to
monitor the toggle bits and DQ5 and DQ13 through
successive read cycles, determining the status as de-
scribed in the previous paragraph. Alternatively, it may
choose to perform other system tasks. In this case, the
system must start at the beginning of the algorithm
when it returns to determine the status of the opera-
tion (top of Figure 8).
DQ5 and DQ13: Exceeded Timing Limits
DQ5 indicates whether the program, erase, or
write-to-buffer time has exceeded a specified internal
pulse count limit. Under these conditions DQ5 and DQ13
produce a “1,” indicating that the program or erase cycle
was not successfully completed.
The device may output a “1” on DQ5 and/or DQ13 if
the system tries to program a “1” to a location that was
previously programmed to “0.” Only an erase opera-
tion can change a “0” back to a “1.” Under this con-
dition, the device halts the operation, and when the
timing limit has been exceeded, DQ5 and/or DQ13
produces a “1.”
In all these cases, the system must write the reset
command to return the device to the reading the array
(or to erase-suspend-read if the device was previously
in the erase-suspend-program mode).
DQ3 and DQ11: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 and DQ11 to deter mine
whether or not erasure has begun. (The sector erase
timer does not apply to the chip erase command.) If
additional sectors are selected for erasure, the entire
time-out also applies after each additional sector
erase command. When the time-out period is com-
plete, DQ3 and DQ11 switch from a “0” to a “1.” If the
time between additional sector erase commands from
the system can be assumed to be less than 50 µs, the
system need not monitor DQ3 and DQ11. See also the
Sector Erase Command Sequence
After the sector erase command is written, the system
should read the status of DQ7 and DQ15 (Data# Poll-
ing) or DQ6 and DQ14 (Toggle Bits I) to ensure that
the device has accepted the command sequence, and
then read DQ3 and DQ11. If DQ3 and DQ11 are “1,”
the Embedded Erase algorithm has begun; all further
commands (except Erase Suspend) are ignored until
the erase operation is complete. If DQ3 and DQ11 are
“0,” the device will accept additional sector erase com-
mands. To ensure the command has been accepted,
the system software should check the status of DQ3
and DQ11 prior to and following each subsequent sec-
tor erase command. If DQ3 and DQ11 are high on the
section.
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