IA186EM-PQF100I-R INNOVASIC [InnovASIC, Inc], IA186EM-PQF100I-R Datasheet - Page 60

• Manufacturer Part Number: IA186EM-PQF100I-R
• Description: 8/16-Bit Microcontrollers
• Manufacturer: INNOVASIC [InnovASIC, Inc]

IA186EM/IA188EM
8/16-BIT Microcontrollers
The three most significant bits of the address bus (a19 – a17) start with their normal function on power-
on reset, permitting the processor to begin fetching instructions from the boot address FFFF0h.
Furthermore, normal function is the default setting for dt/r_n, den_n, and srdy on power-on reset.
s6/clkdiv2_n and uzi_n automatically return to normal operation in the event that the ad15-ad0 bus
override is enabled. The ad15-ad0 bus override is enabled if the bhe_n/aden_n for the IA186EM, or the
rfsh2_n/aden_n for the IA188EM, is held low during power-on reset.
Pin Descriptions
a19 (pio9), a18 (pio8), a17 (pio7), a16 – a0 Address Bus (synchronous outputs with tristate)
These pins are the system’s source of non-multiplexed I/O or memory addresses and occur a half
CLKOUTA cycle before the multiplexed address/data bus (ad15-ad0 for the IA186EM or ao15_ao8 and
ad7-ad0 for the AI188EM). The address bus is tristated during a bus hold or reset.
ad15 – ad8 IA186EM Address/Data bus (level-sensitive synchronous inouts with tristate)
These pins are the system’s source of time-multiplexed I/O or memory addresses and data. The address
function of these pins can be disabled. (See bhe_n/aden_n pin description.) If the address function of
these pins is enabled, the address will be present on this bus during t
present during t
If whb_n is not active, these pins are tristated during t
The address/data bus is tristated during a bus hold or reset.
These pins can be used to load the internal Reset Configuration register (RESCON, offset 0F6h) with
configuration data during a power-on reset.
ad7 – ad0 Address/Data bus (level-sensitive synchronous inouts with tristate)
These pins are the system’s source of time-multiplexed low-order byte of the addresses for I/O or memory
and 8-bit data. The low-order address byte will be present on this bus during t
bit data will be present during t
The address function of these pins can be disabled. (See bhe_n/aden_n pin description.)
If wlb_n is not active, these pins are tristated during t
tristated during a bus hold or reset.
ao15 – ao8 IA188EM Address-only bus (level-sensitive synchronous outputs with tristate)
The address-only bus will contain valid high-order address bits during the bus cycle (t
bus is enabled.
These pins are combined with ad7-ad0 to complete the multiplexed address bus and are tristated during a
bus hold or reset condition.
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel [phone] • Fax [phone] • www.Innovasic.com
2
, t
3
, and t
4
of the same bus cycle.
2
, t
3
, and t
4
of the same bus cycle.
2
2
, t
, t
3
As of Production Version -03
3
, and t
, and t
4
4
of the bus cycle. The address/data bus is
of the bus cycle.
1
of the bus cycle and data will be
1
of the bus cycle and the 8-
1
, t
2
Data Sheet
, t
3
, and t
4
) if the