IA186EM-PQF100I-R INNOVASIC [InnovASIC, Inc], IA186EM-PQF100I-R Datasheet - Page 61

• Manufacturer Part Number: IA186EM-PQF100I-R
• Description: 8/16-Bit Microcontrollers
• Manufacturer: INNOVASIC [InnovASIC, Inc]

IA186EM/IA188EM
8/16-BIT Microcontrollers
ale Address Latch Enable (synchronous output)
This signal indicates the presence of an address on the address bus (ad15-ad0 for the IA186EM or ao15-
ao8 and ad7-ad0 for the AI188EM), which is guaranteed to be valid on the falling edge of ale.
ardy Asynchronous Ready (level-sensitive asynchronous input)
This asynchronous signal provides an indication to the microcontroller that the addressed I/O device or
memory space will complete a data transfer. This active high signal is asynchronous with respect to
clkouta and if the falling edge of ardy is not synchronized to clkouta and additional clock cycle may be
added
ardy should be tied high to maintain a permanent assertion of the ready condition. On the other hand, if
the ardy signal is not used by the system it should be tied low, which passes control to the srdy signal.
bhe_n/aden_n IA186EM only Bus High Enable (synchronous output with tristate) /Address Enable
(input with internal pull-up)
bhe_n - bhe_n and address bit ad0 or a0 inform the system which bytes of the data bus (upper, lower, or
both) are involved in the current memory access bus cycle as shown in the following table.
bhe_n does not require latching and during bus hold and reset is tristated. It is asserted during t
remains so through t
The high and low byte write enable functions of bhe_n and ad0 are performed by whb_n and wlb_n
respectively.
When using the ad bus, DRAM refresh cycles are indicated by bhe_n/aden_n and ad0 both being high.
During refresh cycles the a and ad busses may not have the same address during the address phase of the
ad bus cycle necessitating the use of ad0 as a determinant for the refresh cycle rather than A0.
An additional signal is utilized for PSRAM refreshes (see mcs3_n/rfsh_n pin description).
aden_n
There is a weak internal pull-up on bhe_n/aden_n obviating the need for an external pull-up and reducing
power consumption.
Holding aden_n high or letting it float during power-on reset passes control of the address function of the
ad bus (ad15-ad0) during LCS and UCS bus cycles from aden_n to the DA bit in LMCS and UMCS
registers. When the address function is selected, the memory address is placed on the a19-a0 pins.
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel [phone] • Fax [phone] • www.Innovasic.com
3
and t
bhe_n
0
0
1
1
w
.
ad0
0
1
0
1
Word Transfer
High-Byte Transfer (Bits 15-8)
Low-Byte Transfer (Bits 7-0)
Refresh
As of Production Version -03
Type of Bus Cycle
Data Sheet
1
and