HY57V281620ELT Hynix Semiconductor, HY57V281620ELT Datasheet - Page 10

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HY57V281620ELT

Manufacturer Part Number
HY57V281620ELT
Description
128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O
Manufacturer
Hynix Semiconductor
Datasheet
AC CHARACTERISTICS I
Note:
1. Assume t
2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 0.2V. If t
Rev. 1.1 / Jan. 2005
System Clock
Cycle Time
Clock High Pulse Width
Clock Low Pulse Width
Access Time
From Clock
Data-out Hold Time
Data-Input Setup Time
Data-Input Hold Time
Address Setup Time
Address Hold Time
CKE Setup Time
CKE Hold Time
Command Setup Time
Command Hold Time
CLK to Data Output in Low-Z Time
CLK to
Data Output
in High-Z Time
then (t
R
/2-0.5)ns should be added to the parameter.
R
/ t
F
Parameter
(input rise and fall time) is 1ns. If t
CAS
Latency=3
CAS
Latency=2
CAS
Latency=3
CAS
Latency=2
CAS
Latency=3
CAS
Latency=2
(AC operating conditions unless otherwise noted)
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CK3
CK2
CHW
CLW
AC3
AC2
OH
DS
DH
AS
AH
CKS
CKH
CS
CH
OLZ
OHZ3
OHZ2
Sym-
bol
R
& t
F
Synchronous DRAM Memory 128Mbit (8Mx16bit)
> 1ns, then [(t
1.75
1.75
Min Max Min Max Min Max Min Max
5.0
2.0
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1.0
10
-
-
-
-
5
1000
4.5
6.0
4.5
6.0
-
-
-
-
-
-
-
-
-
-
-
-
R
6.0
2.0
2.0
2.0
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1.0
+t
10
-
-
-
-
F
)/2-1]ns should be added to the parameter.
6
1000
5.4
6.0
5.4
6.0
-
-
-
-
-
-
-
-
-
-
-
-
HY57V281620E(L)T(P) Series
7.0
2.0
2.0
2.5
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1.5
10
-
-
-
-
R
> 1ns,
7
1000
5.4
6.0
5.4
6.0
-
-
-
-
-
-
-
-
-
-
-
-
7.5
2.5
2.5
2.5
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1.5
10
-
-
-
-
H
1000
5.4
6.0
5.4
6.0
-
-
-
-
-
-
-
-
-
-
-
-
Unit Note
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
2
1
1
1
1
1
1
1
1
10

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