82V3352EDG IDT [Integrated Device Technology], 82V3352EDG Datasheet - Page 113
82V3352EDG
Manufacturer Part Number
82V3352EDG
Description
SYNCHRONOUS ETHERNET WAN PLL
Manufacturer
IDT [Integrated Device Technology]
Datasheet
1.82V3352EDG.pdf
(125 pages)
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Table 48: Input/Output Clock Timing
8.6
Electrical Specifications
Note:
1. Typical delay provided as reference only.
IDT82V3352
The inputs and outputs are aligned ideally. But due to the circuit delays, there is delay between the inputs and outputs.
INPUT / OUTPUT CLOCK TIMING
Symbol
t
t
t
t
t
t
1
2
3
4
5
6
19.44 MHz Output Clock
19.44 MHz Input Clock
8 kHz Input Clock
8 kHz Output Clock
51.84 MHz Input Clock
51.84 MHz Output Clock
6.48 MHz Input Clock
6.48 MHz Output Clock
38.88 MHz Output Clock
25.92 MHz Input Clock
38.88 MHz Input Clock
25.92 MHz Output Clock
Figure 22. Input / Output Clock Timing
Typical Delay
1.4
t
t
t
t
t
t
1
4
1
1
2
3
2
3
4
5
6
1
(ns)
113
SYNCHRONOUS ETHERNET WAN PLL
Peak to Peak Delay Variation (ns)
1.6
1.6
1.6
1.6
1.6
1.6
March 23, 2009
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