82V3352EDG IDT [Integrated Device Technology], 82V3352EDG Datasheet - Page 76
82V3352EDG
Manufacturer Part Number
82V3352EDG
Description
SYNCHRONOUS ETHERNET WAN PLL
Manufacturer
IDT [Integrated Device Technology]
Datasheet
1.82V3352EDG.pdf
(125 pages)
- Current page: 76 of 125
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IN_FREQ_READ_STS - Input Clock Frequency Read Value
Programming Information
IDT82V3352
Address: 42H
Type: Read
Default Value: 00000000
IN_FREQ_VAL
7 - 0
Bit
UE7
7
IN_FREQ_VALUE[7:0]
IN_FREQ_VAL
Name
UE6
6
These bits represent a 2’s complement signed integer. If the value is multiplied by the value in the
FREQ_MON_FACTOR[3:0] bits (b3~0, 2EH), the frequency of an input clock with respect to the reference clock in ppm will
be gotten. The input clock is selected by the IN_FREQ_READ_CH[3:0] bits (b3~0, 41H).
The value in these bits is updated every 16 seconds, starting when an input clock is selected.
IN_FREQ_VAL
UE5
5
IN_FREQ_VAL
UE4
4
76
IN_FREQ_VAL
UE3
3
Description
IN_FREQ_VAL
UE2
2
SYNCHRONOUS ETHERNET WAN PLL
IN_FREQ_VAL
UE1
1
IN_FREQ_VAL
March 23, 2009
UE0
0
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