82V3352EDG IDT [Integrated Device Technology], 82V3352EDG Datasheet - Page 39
82V3352EDG
Manufacturer Part Number
82V3352EDG
Description
SYNCHRONOUS ETHERNET WAN PLL
Manufacturer
IDT [Integrated Device Technology]
Datasheet
1.82V3352EDG.pdf
(125 pages)
- Current page: 39 of 125
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4
registers in the device. The microprocessor interface supports Serial
mode only.
When CLKE is asserted low, data on SDO will be clocked out on the ris-
Microprocessor Interface
IDT82V3352
The microprocessor interface provides access to read and write the
In a read operation, the active edge of SCLK is selected by CLKE.
MICROPROCESSOR INTERFACE
SCLK
SDI
SDO
SDO
CS
SCLK
SDI
CS
t
t
su2
su1
R/ W
R/ W
t
Figure 14. Serial Read Timing Diagram (CLKE Asserted High)
Figure 13. Serial Read Timing Diagram (CLKE Asserted Low)
h1
A0
A0
A1
A1
A2
High-Z
A2
High-Z
t
pw1
A3
A3
t
pw2
A4
A4
A5
A5
39
A6
A6
ing edge of SCLK. When CLKE is asserted high, data on SDO will be
clocked out on the falling edge of SCLK.
of SCLK.
t
d1
In a write operation, data on SDI will be clocked in on the rising edge
t
d1
D0
D0
D1
D1
D2
D2
D3
D3
SYNCHRONOUS ETHERNET WAN PLL
D4
D4
D5
D5
D6
D6
t
d2
t
h2
t
D7
t
d2
D7
h2
March 23, 2009
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