82V3352EDG IDT [Integrated Device Technology], 82V3352EDG Datasheet - Page 6

• Manufacturer Part Number: 82V3352EDG
• Description: SYNCHRONOUS ETHERNET WAN PLL
• Manufacturer: IDT [Integrated Device Technology]

List of Figures
Figure 1. Functional Block Diagram .............................................................................................................................................................................. 9
Figure 2. Pin Assignment (Top View) .......................................................................................................................................................................... 10
Figure 3. Pre-Divider for An Input Clock ..................................................................................................................................................................... 17
Figure 4. Input Clock Activity Monitoring ..................................................................................................................................................................... 18
Figure 5. External Fast Selection ................................................................................................................................................................................ 20
Figure 6. T0 Selected Input Clock vs. DPLL Automatic Operating Mode ................................................................................................................... 26
Figure 7. On Target Frame Sync Input Signal Timing ................................................................................................................................................. 34
Figure 8. 0.5 UI Early Frame Sync Input Signal Timing .............................................................................................................................................. 34
Figure 9. 0.5 UI Late Frame Sync Input Signal Timing ............................................................................................................................................... 35
Figure 10. 1 UI Late Frame Sync Input Signal Timing ................................................................................................................................................. 35
Figure 11. IDT82V3352 Power Decoupling Scheme ................................................................................................................................................... 37
Figure 12. Line Card Application ................................................................................................................................................................................. 38
Figure 13. Serial Read Timing Diagram (CLKE Asserted Low) ................................................................................................................................... 39
Figure 14. Serial Read Timing Diagram (CLKE Asserted High) .................................................................................................................................. 39
Figure 15. Serial Write Timing Diagram ....................................................................................................................................................................... 40
Figure 16. JTAG Interface Timing Diagram ................................................................................................................................................................. 41
Figure 17. Recommended PECL Input Port Line Termination .................................................................................................................................. 106
Figure 18. Recommended PECL Output Port Line Termination ................................................................................................................................ 106
Figure 19. Recommended LVDS Input Port Line Termination .................................................................................................................................. 108
Figure 20. Recommended LVDS Output Port Line Termination ................................................................................................................................ 108
Figure 21. Output Wander Generation ...................................................................................................................................................................... 112
Figure 22. Input / Output Clock Timing ...................................................................................................................................................................... 113
Figure 23. 64-Pin PP Package Dimensions (a) (in Millimeters) ................................................................................................................................. 120
Figure 24. 64-Pin PP Package Dimensions (b) (in Millimeters) ................................................................................................................................. 121
Figure 25. 64-Pin EDG Package Dimensions (a) (in Millimeters) .............................................................................................................................. 122
Figure 26. 64-Pin EDG Package Dimensions (b) (in Millimeters) .............................................................................................................................. 123
Figure 27. EDG64 Recommended Land Pattern with Exposed Pad (in Millimeters) ................................................................................................. 124
List of Figures
6
March 23, 2009