82V3352EDG IDT [Integrated Device Technology], 82V3352EDG Datasheet - Page 67
82V3352EDG
Manufacturer Part Number
82V3352EDG
Description
SYNCHRONOUS ETHERNET WAN PLL
Manufacturer
IDT [Integrated Device Technology]
Datasheet
1.82V3352EDG.pdf
(125 pages)
- Current page: 67 of 125
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IN1_IN2_DIFF_SEL_PRIORITY_CNFG - Differential Input Clock 1 & 2 Priority Configuration *
Programming Information
Address: 28H
Type: Read / Write
Default Value: 00000000
IDT82V3352
IN2_DIFF_SEL_
PRIORITY3
7 - 4
3 - 0
Bit
7
INn_DIFF_SEL_PRIORITY[3:0]
INn_DIFF_SEL_PRIORITY[3:0]
IN2_DIFF_SEL_
PRIORITY2
Name
6
IN2_DIFF_SEL_
PRIORITY1
5
These bits set the priority of the corresponding INn_DIFF. Here n is 2.
0000: Disable INn_DIFF for automatic selection. (default)
0001: Priority 1.
0010: Priority 2.
0011: Priority 3.
0100: Priority 4.
0101: Priority 5.
0110: Priority 6.
0111: Priority 7.
1000: Priority 8.
1001: Priority 9.
1010: Priority 10.
1011: Priority 11.
1100: Priority 12.
1101: Priority 13.
1110: Priority 14.
1111: Priority 15.
These bits set the priority of the corresponding INn_DIFF. Here n is 1.
0000: Disable INn_DIFF for automatic selection. (default)
0001: Priority 1.
0010: Priority 2.
0011: Priority 3.
0100: Priority 4.
0101: Priority 5.
0110: Priority 6.
0111: Priority 7.
1000: Priority 8.
1001: Priority 9.
1010: Priority 10.
1011: Priority 11.
1100: Priority 12.
1101: Priority 13.
1110: Priority 14.
1111: Priority 15.
IN2_DIFF_SEL_
PRIORITY0
4
67
IN1_DIFF_SEL_
PRIORITY3
3
Description
IN1_DIFF_SEL_
PRIORITY2
2
SYNCHRONOUS ETHERNET WAN PLL
IN1_DIFF_SEL_
PRIORITY1
1
IN1_DIFF_SEL_
March 23, 2009
PRIORITY0
0
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