82V3352EDG IDT [Integrated Device Technology], 82V3352EDG Datasheet - Page 48

• Manufacturer Part Number: 82V3352EDG
• Description: SYNCHRONOUS ETHERNET WAN PLL
• Manufacturer: IDT [Integrated Device Technology]

NOMINAL_FREQ[15:8]_CNFG - Crystal Oscillator Frequency Offset Calibration Configuration 2
NOMINAL_FREQ[23:16]_CNFG - Crystal Oscillator Frequency Offset Calibration Configuration 3
Programming Information
IDT82V3352
Address: 05H
Type: Read / Write
Default Value: 00000000
Address: 06H
Type: Read / Write
Default Value: 00000000
7 - 0
7 - 0
Bit
Bit
NOMINAL_FRE
NOMINAL_FRE
Q_VALUE23
Q_VALUE15
NOMINAL_FREQ_VALUE[23:16]
NOMINAL_FREQ_VALUE[15:8] Refer to the description of the NOMINAL_FREQ_VALUE[23:16] bits (b7~0, 06H).
7
7
Name
Name
NOMINAL_FRE
NOMINAL_FRE
Q_VALUE22
Q_VALUE14
6
6
The NOMINAL_FREQ_VALUE[23:0] bits represent a 2’s complement signed integer. If the value is multiplied by
0.0000884, the calibration value for the master clock in ppm will be gotten.
For example, the frequency offset on OSCI is +3 ppm. Though -3 ppm should be compensated, the calibration value is
calculated as +3 ppm:
3 ÷ 0.0000884 = 33937 (Dec.) = 8490 (Hex);
So ‘008490’ should be written into these bits.
The calibration range is within ±741 ppm.
NOMINAL_FRE
NOMINAL_FRE
Q_VALUE21
Q_VALUE13
5
5
NOMINAL_FRE
NOMINAL_FRE
Q_VALUE20
Q_VALUE12
4
4
48
NOMINAL_FRE
NOMINAL_FRE
Q_VALUE19
Q_VALUE11
3
3
Description
Description
NOMINAL_FRE
NOMINAL_FRE
Q_VALUE18
Q_VALUE10
2
2
SYNCHRONOUS ETHERNET WAN PLL
NOMINAL_FRE
NOMINAL_FRE
Q_VALUE17
Q_VALUE9
1
1
March 23, 2009
NOMINAL_FRE
NOMINAL_FRE
Q_VALUE16
Q_VALUE8
0
0