MT90502_06 ZARLINK [Zarlink Semiconductor Inc], MT90502_06 Datasheet - Page 104

• Manufacturer Part Number: MT90502_06
• Description: Multi-Channel AAL2 SAR
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

2.10.3
Bit-wise means that every bit of HDLC data coming from the H.100/H.110 bus is examined. A control flag of 7Eh
("01111110") is used to signify the start and end of a packet. When using this form of HDLC, each HDLC packet
must begin with a flag and end with a flag, although a single flag may represent both the end of a packet and the
beginning of another. A '0' is inserted after every 5 '1's of incoming data (called zero insertion) to differentiate the
control flag and data. If neither flags nor data are being transmitted onto the bus, the idle code is transmitted. The
idle code is an endless string of '1's. Note that a valid idle code must be at least 7-bits long (7 '1's).
2.10.4
Byte-wise HDLC format also employs "01111110" (7Eh) as a control flag. A 7Eh payload value is replaced by two
bytes - 7Dh and 5Eh, while a 7Dh payload value is replaced by two bytes - 7Dh and 5Dh. A single flag may
represent both the end of a packet and the beginning of another. This flag is put into the TX circular buffer with the
data. When no data is being transmitted onto the bus, the flag character is sent repeatedly until data is transmitted
again.
2.11
2.11.1
The location of the absolute starting and ending addresses of the internal and external memories are shown in
Table 34. The complete set of internal registers is listed in Section 3.0, “Register List,” on page 114. The beginning
and ending addresses of the various structure spaces in SSRAM and SDRAM are listed in Section 2.11.2, “Memory
Structures,” on page 105.
Memory
Memory Map
HDLC Bit-Wise Format
HDLC Byte-Wise Format
Start Address
0100h
0200h
0300h
0400h
0500h
0600h
0700h
0800h
0900h
1000h
1300h
1400h
2000h
2100h
2200h
2300h
2400h
End Address
Table 34 - MT90502 Memory Map
01FEh
02FEh
03FEh
04FEh
05FEh
06FEh
07FEh
08FEh
09FEh
11FEh
13FEh
15FEh
20FEh
21FEh
22FEh
23FEh
24FEh
Zarlink Semiconductor Inc.
MT90502
104
SID Byte to Silence Buffer Memory
UTOPIA Port C Input FIFO
UTOPIA Port A Input FIFO
UTOPIA Port B Input FIFO
Tone Data Buffer Memory
TX SAR Input FIFO
AAL0 Input FIFO
PCM Law Table
rxtdmreg
txtdmreg
h100reg
mainreg
miscreg
cpureg
utoreg
Name
rxreg
txreg
Data Sheet