MT90502_06 ZARLINK [Zarlink Semiconductor Inc], MT90502_06 Datasheet - Page 125

• Manufacturer Part Number: MT90502_06
• Description: Multi-Channel AAL2 SAR
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Address: 224h
Label: txc_clk_gen
Reset Value: 0403h
txc_clk_div[5:0]
txc_clk_divisor_load_now
txc_clk_inv
txc_clk_src[2:0]
txc_clk_oe
txc_clk_present
txc_clk_divisor_reset
reserved
Label
Bit Position
Table 54 - Tx C Clock Division Register
15:14
10:8
5:0
11
12
13
6
7
Zarlink Semiconductor Inc.
Type
PUL
RW
RW
RW
RW
RW
RW
RW
MT90502
125
This bit, when written to '1', will force the new txc_clk_div
txc_clk clock source division value. The txc_clk clock
source (selected using txc_clk_src) can be divided before
being sent out on UTOPIA. Note that odd values will force
the duty cycle to be maintained, rather than returning it to
50-50.
to be applied immediately (possibly causing glitches on
the txc_clk). This bit should only be set to one when
loading the divisor when the txc_clk_present bit is cleared.
Note that it is possible to dynamically change the divisor
value without causing glitches on the output clock if this bit
is not written to 1.
When '1', the txc_clk's source will be inverted before being
driven out on the txc_clk pin.
“000”=txa_clk_in; “001”=txb_clk_in; ”010”=txc_clk_in;
“011”=rxa_clk_in; “100”=rxb_clk_in; “101”=rxc_clk_in;
“110”=mem_clk; others = reserved.
txc_clk output enable. Active high.
Set to '1' when the txc_clk is present. If the user does not
want to use the txa UTOPIA interface, this bit should be
left at '0' regardless of the presence of the txc_clk.
When '0', will reset the clock division.
Reserved. Must always be “00”
Description
Data Sheet