MT90502_06 ZARLINK [Zarlink Semiconductor Inc], MT90502_06 Datasheet - Page 185

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MT90502_06

Manufacturer Part Number
MT90502_06
Description
Multi-Channel AAL2 SAR
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
4.2
4.3
t1_non_muxed write_access_active falling edge to
t1_writes
t2_non_muxed cpu_rdy_ndtack rising edge to
t2_writes1
t2_writes2
t4
t5
t6
Symbol
AC Characteristics
Intel/Motorola Interface
cpu_a[14:0]/cpu_a_das
write_access_active
(when both CS and WR are low)
cpu_rdy_ndtack
cpu_a valid
cpu_a_das valid
write_access_active falling edge to cpu_d
valid
cpu_a invalid
cpu_a_das invalid
cpu_rdy_ndtack rising edge to
write_access_active rising edge
cpu_rdy_ndtack rising edge to cpu_d
invalid
write_access_active falling edge to
cpu_rdy_ndtack falling edge
Write Access Time
write_access_active rising edge to
cpu_rdy_ndtack tri-state
Table 202 - Non-Multiplexed CPU Interface - Intel Mode - Write Access
cpu_d[15:0]
Figure 71 - Non-Multiplexed CPU Interface - Intel Mode - Write Access
Description
t1_non_muxed
Zarlink Semiconductor Inc.
t4
MT90502
t1_writes
185
0
0
0
0
0
Min.
t5
t2_non_muxed
t2_writes2
Typical
t2_writes1
2 * upclk - 4
2 * upclk - 4
Max.
740
12
10
t6
Data Sheet
ns
ns
ns
ns
ns
ns
ns
ns
Unit

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