MT90502_06 ZARLINK [Zarlink Semiconductor Inc], MT90502_06 Datasheet - Page 133

• Manufacturer Part Number: MT90502_06
• Description: Multi-Channel AAL2 SAR
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

3.3
Address: 25Ah
Label: sdram_conf5
Reset Value: 003Fh
sdram_we_man
reserved
Address: 300h
Label: control
Reset Value: 0000h
scanning_enable
aal0_cell_written
reserved
test_status
Address: 302h
Label: status0
Reset Value: 0000h
aal0_cell_fifo_empty
reserved
TX Registers
Label
Label
Label
Bit Position
Bit Position
Bit Position
14:2
15:1
15
15:6
0
1
0
5
Table 68 - SDRAM Configuration Register 5
Table 69 - TX Control Register
Type
Type
ROL When '1', CPU can write another 4 AAL0 cells to internal FIFO
ROL Reserved. Always read as “0000_0000_0000_000”
PUL Written to '1' after an AAL0 cell has been written by the CPU to the
Table 70 - TX Status Register
RW
RW
TS
Type
RW
RW
Zarlink Semiconductor Inc.
When '1', the cell time-out scanning process is enabled and will
send cells beyond a certain pending time (programmed per VC).
TX AAL0 Cell FIFO. The cell will then be automatically sent.
Reserved. Must always be “0000_0000_0000_0”
Reserved. Must always be “0”.
MT90502
While sdram_enable is '0', the value placed in this register will
be put on the we line for 1 cycle if sdram_manual_access is
written to '1'.
Reserved. Must always be “0000_0000_00”
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Data Sheet