MT90502_06 ZARLINK [Zarlink Semiconductor Inc], MT90502_06 Datasheet - Page 181

• Manufacturer Part Number: MT90502_06
• Description: Multi-Channel AAL2 SAR
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

3.9
Address: 900h
Label: control
Reset Value: 0000h
hdlc_type
rx_tdm_time_slot_lead
number_packets_per_frame
reserved
llman_process_enable
u_law_zero_illegal
padding_law
test_status
Address: 902h
Label: status0
Reset Value: 0000h
llman_process_crashed
underrun_detect
underrun_wrap_detect
rxtdm_read_cache_overflow
rxtdm_write_cache_overflow
write_back_cache_overflow
rx_tdm_fifo_overflow
rxsar_pointer_wb_overflow
reserved
RX TDM Registers
Label
Label
Position Type
Bit Position Type
15:8
Bit
0
1
2
3
4
5
6
7
11:10
3:1
6:4
Table 199 - RX TDM Status Register 0
15
Table 198 - RX TDM Control Register
0
7
8
9
ROL Indicates that the linked-list manager crashed. This indicates corrupt
ROL Underrun detected on a channel.
ROL Indicates that the 16-bit underrun counter on a single channel has
ROL Overflow in the RX TDM read cache. Fatal chip error.
ROL Overflow in the RX TDM write cache. Fatal chip error.
ROL Overflow in the RX TDM write back cache.
ROL Overflow in the RX TDM data FIFO. Fatal chip error.
ROL Overflow in the RX SAR pointer write back FIFO. Fatal chip error.
ROL Reserved. Always read as “0000_0000”
RW 0'=Bit wise HDLC Framing; '1'=Byte Wise HDLC Framing.
RW Set to “111” for normal operation.
RW “000” = 32 packets, “001” = 64 packets, “010” = 128 packets,
RW Reserved. Must always be “0”.
RW Enables the treatment of incoming RX SAR bytes going to the
RW When '1', the u-law value 00h will be replaced by 02h.
RW “00” = don't translate padding, OL bit in Rx TDM Control
data in the linked list memory.
wrapped.
TS Reserved. Must always be “0”.
Zarlink Semiconductor Inc.
MT90502
“011” = 256 packets, “100” = 512 packets, “101” = 1024, “11x”
= reserved
H100 bus.
Structure is ignored for padding bytes; “01” = padding is in
u-law only, “10” = padding is in A-law only.
181
Description
Description
Data Sheet