MT90502_06 ZARLINK [Zarlink Semiconductor Inc], MT90502_06 Datasheet - Page 189
MT90502_06
Manufacturer Part Number
MT90502_06
Description
Multi-Channel AAL2 SAR
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
1.MT90502_06.pdf
(205 pages)
- Current page: 189 of 205
- Download datasheet (2Mb)
Note: t1, t4, and t5 are dependent upon the last of cpu_cs and cpu_rd_ds to be asserted. t6 is dependent on the
first of cpu_cs and cpu_rd_ds to be de-asserted.
Sym.
Sym.
t12
t10
t12
t11
t11
t1
t3
t4
t5
t6
t7
t1
t3
t4
t5
t6
t7
t9
Address & Data Setup -- cpu_cs and cpu_rd_ds asserted to
cpu_a[14:0] and cpu_d[15:0] and cpu_a_das valid
Address & Data Hold -- cpu_rdy_ndtack low to cpu_a[14:0]
and cpu_d[15:0] and cpu_a_das invalid
cpu_rdy_ndtack high -- cpu_cs and cpu_rd_ds asserted to
cpu_rdy_ndtack driving one
cpu_rdy_ndtack delay -- cpu_cs and cpu_rd_ds asserted to
cpu_rdy_ndtack driving zero
cpu_rdy_ndtack hold -- cpu_cs and cpu_rd_ds de-asserted
to cpu_rdy_ndtack driving one
cpu_rdy_ndtack high impedance -- cpu_rdy_ndtack driving
one to cpu_rdy_ndtack high impedance
cpu_r/w low to both cpu_cs and cpu_ds asserted
cpu_cs or cpu_ds high to cpu_r/w high
Address Setup -- cpu_cs and cpu_rd_ds asserted to
cpu_a[14:0] and cpu_a_das valid
Address Hold -- cpu_rdy_ndtack low to cpu_a[14:0] and
cpu_a_das invalid
cpu_rdy_ndtack high -- cpu_cs and cpu_rd_ds asserted to
cpu_rdy_ndtack driving one
cpu_rdy_ndtack delay -- cpu_cs and cpu_rd_ds asserted to
cpu_rdy_ndtack asserted
cpu_rdy_ndtack hold -- cpu_cs or cpu_rd_ds de-asserted to
cpu_rdy_ndtack driving one
cpu_rdy_ndtack high impedance -- cpu_rdy_ndtack driving
one to cpu_rdy_ndtack high-impedance
Data to cpu_rdy_ndtack delay -- cpu_d[15:0] valid to
cpu_rdy_ndtack asserted
Data output hold -- cpu_cs or cpu_rd_ds de-asserted to
cpu_d[15:0] invalid
cpu_r/w high to both cpu_cs and cpu_ds asserted
cpu_cs or cpu_ds high to cpu_r/w low
Table 204 - Non-Multiplexed CPU Interface - Motorola Mode
Description Write Access
Description Read Access
Zarlink Semiconductor Inc.
MT90502
189
upclk - 4
Min.
Min.
0
0
0
2
0
0
0
0
0
2
0
0
0
Typ.
Typ.
See Table 205,
“t5 Read
Access Times,”
on page 190.
2*upclk - 4
2*upclk - 4
Max.
Max.
740
12
10
12
10
10
8
8
Data Sheet
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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