MT90502_06 ZARLINK [Zarlink Semiconductor Inc], MT90502_06 Datasheet - Page 61

• Manufacturer Part Number: MT90502_06
• Description: Multi-Channel AAL2 SAR
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

2.4.6
Data cells, such as those containing OAM information, are placed in a programmable length FIFO in external
memory. The length of the FIFO is stored in register 430h. The CPU can read one or more data cells from the FIFO
at any time, after obtaining the address of the FIFO (register 430h) and the read pointer (register 432h). The CPU is
responsible for updating the read pointer following each read. The write pointer, incremented by hardware,
indicates the location where the next data cell will be written. The FIFO is empty is the read pointer points to the
same location as the write pointer.
The CPU can be alerted to the presence of data cells via an interrupt that triggers if either of two events occur:
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•
When ready to process the information, the CPU obtains a read pointer to the information from register 432h and
reads the information through 26-word accesses.
Cells with the OAM bit set in the PTI portion of the header can be directed to the data cell FIFO on a per VC basis.
The same is true for non-OAM cells. In addition, unknown non-OAM cells and/or unknown OAM cells can also be
sent to the data cell FIFO. All unknown non-OAM cells are directed to the same location(s), and all unknown OAM
cells are directed to the same location(s).
2.4.7
An Error/Event Report FIFO exists in RX SSRAM whose base address and size are configured through register
438h. Four types of structures, as shown in Figure 26, are available to cover all errors or events listed in Table 24.
Once an error or event occurs, a corresponding 4-word structure will be generated and written into Report FIFO.
The error/event structure contains all the details pertaining to that error or event.
Similar to the data cell FIFO, the CPU can read the error/event FIFO at any time after obtaining the base address
(register 438h) and the read pointer of the error/event FIFO (register 43Ch). Again, an interrupt can be generated
that triggers if either of two events occur. Those events are
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•
When ready to process the information, the CPU obtains a read pointer to the information from register 43Ch and
reads the information through 4-word accesses.
Note: Both PCM and HDLC CPS-Packets will generate a report structure when they are initialized. Apart from the
generation of the error report structure, no action is taken on errors/events.
the interrupt can be generated when the FIFO becomes more than half full, or
the interrupt can be generated if a data cell has been present in the FIFO for longer than a programmable
period of time (registers 460h, 462h).
the FIFO becomes more than half full, or
an error/event report structure has been present in the FIFO for longer than a programmable period of
time (registers 464h, 466h).
Treatment of Data Cells
Errors and Events
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MT90502
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Data Sheet