MT90502_06 ZARLINK [Zarlink Semiconductor Inc], MT90502_06 Datasheet - Page 74

• Manufacturer Part Number: MT90502_06
• Description: Multi-Channel AAL2 SAR
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

2.6.5.3
A LUT base address and size exists for each of the three ports (registers 620h, 640h, 660h). The number of entries
in the LUT, given by its size, ranges from 17 bits to 20 bits (128 K to 1024 K entries). A 17- to 20-bit identifier for
each entry is created by concatenating the LSBs from the VPI field with LSBs from the VCI field of a cell header.
The number of VCI LSBs to be used as the LSBs in the identifier is programmed in registers 622h, 642h and 662h
for Port A, B and C, respectively. The remaining MSBs of the identifier are taken from the LSBs of the VPI field. This
concatenated value is then multiplied by 8 (insert three LSB zeros). The result, when added to the LUT base
address, will point to the base address of the LUT structure for this cell. The LUT, shown in Figure 37 will determine
the routing and/or header translation of the cell.
+8*(N-3)
+8*(N-2)
+8*(N-1)
LUT A,B, and C structures are 8-bytes in size located in SDRAM at varying base addresses depending on the number of
channels used.
Fields in Plain are written by the CPU/Software.
NCR:
OCR:
A & B:
VC Number: Points to the RX Disassembly Structure to which this cell corresponds.
NNI:
VPI:
VCI:
+0000h
+0010h
+0018h
+0018h
N is defined as 2
(Number of considered VPI/VCI bits in
concatenation)
+008h
LUT Addressing
Normal Cell routing. “00000” = discard; “xxxx1” = Send to TXA port; “xxx1x” = Send to TXB port; “xx1xx” = Send to
TXC port; “x1xxx” = Send to data cell FIFO (in external memory); “1xxxx” = Send to RX SAR.
OAM Cell Routing. “0000” = discard; “xxx1” = Send to TXA port; “xx1x” = Send to TXB port; “xx1xx” = Send to TXC
port; “1xxx” = Send to data cell FIFO (in external memory).
Clock recovery reference indicators. When “1”, a pulse will be sent to the clock recovery module indicating that a
reference packet has been received. These two bits correspond to two independent and redundant clock recovery VCs.
Replace the cell VPI [11:8] with the Replacement VPI [11:8] when this bit is “1”.
Replace the cell VPI [7:0] with the Replacement VPI [7:0] when this bit is “1”.
Replace the cell VCI [15:0] with the Replacement VCI [15:0] when this bit is “1”.
v
LUT- N-3
LUT- N-2
LUT- N-1
LUT- 0
LUT- 1
LUT- 2
LUT- 3
LUT- 4
Figure 37 - SDRAM Mapping - Look-Up Tables Structure
RX SAR Disassembly Structure
Reserved
Zarlink Semiconductor Inc.
+0 NNI VPI VCI
+2
+4
+6
+0 0
+2
+4
+6
MT90502
b15 b14 b13 b12 b11 b10 b9 b8
b15 b14 b13 b12 b11 b10 b9 b8
0
74
0
Replacement VCI [11:0]
Replacement VPI [11:0]
A
A
B
B
b7 b6 b5 b4 b3
b7 b6 b5 b4 b3
NCR
NCR
VC Number [9:0]
VCI [15:12]
Data Sheet
b2
b2
OCR
OCR
b1
b1
b0
b0