MT90502_06 ZARLINK [Zarlink Semiconductor Inc], MT90502_06 Datasheet - Page 44

• Manufacturer Part Number: MT90502_06
• Description: Multi-Channel AAL2 SAR
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

2) A CPS-Packet descriptor is written to registers 522h, 524h, and 526h. The value to which each field must be set
is indicated in Figure 17, “CPS-Packet Descriptor Queue,” on page 45.
CPS-Packet base address: Base address of CPS-Packet’s payload bytes. The address is relative to the base
address of bank A. Thus, if payload bytes 0 and 1 of the CPS-Packet are located at address 400126h, then the
address inserted is 00126h.
WB: Set to ‘1’. Write back must be disabled for CPU sourced CPS-Packets.
CID: The value of the CID of the sent CPS-Packet. Any 8-bit value is valid, with the exception of 00h, which is illegal
(AAL2 specification).
CPU: Set to ‘1’. Indicates that the CPS-Packet is sourced by the CPU.
Size: As mentioned earlier, the payload of the TX CPU CPS-Packets can be inserted in any unoccupied portion of
SSRAM bank A. A portion of bank A may be reserved for a virtual buffer. This buffer may be used to store the
payload bytes of all CPU sourced CPS-Packets. In the case where the payload of a CPS-Packet is inserted at the
end of the buffer and wraps to the beginning, the Size field indicates where to wrap to. Take for example a
CPS-Packet of 10 payload bytes, and the Size field set to “0000” (256 bytes). Thus, the CPS-Packet must reside in
a 256 byte boundary of the external memory. Now suppose that the CPS-Packet is written to address 1FEh. This
implies that the payload bytes must be written as follows:
Length: Set to the length of the CPS-Packet, minus 1 (i.e., LI field).
UUI: The value of the UUI field of the sent CPS-Packet. Any 5-bit value is valid.
Note: CPU CPS-Packets sent out on voice CIDs must use UUIs 16-31. They can use all UUIs on management
CIDs (1-7).
3) Once the descriptor is written to the registers, the TX TDM module of the MT90502 is made aware of the
CPS-Packet through register 520h. The VC number of an open AAL2 VC is written in bits [9:0], and the request bit,
bit [10] of the register, is set to ‘1’. Finally, the register is written to. The CPU CPS-Packet has been written when the
request bit of the register is cleared by hardware.
1FEh (word 0):
100h (word 1):
102h (word 2):
104h (word 3):
106h (word 4):
Table 20 - Example of Written Payload Bytes
address
...
Zarlink Semiconductor Inc.
MT90502
44
bits [15:8]
payload 2
payload 4
payload 6
payload 8
payload 0
...
payload 3
payload 5
payload 7
payload 9
payload 1
bits[7:0]
...
Data Sheet