AM79C974KCW AMD [Advanced Micro Devices], AM79C974KCW Datasheet - Page 136
![no-image](/images/no-image-200.jpg)
AM79C974KCW
Manufacturer Part Number
AM79C974KCW
Description
PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems
Manufacturer
AMD [Advanced Micro Devices]
Datasheet
1.AM79C974KCW.pdf
(153 pages)
- Current page: 136 of 153
- Download datasheet (833Kb)
Page 19
(Reprinted as page 9 of this amendment)
PIN DESCRIPTION, GNTA
Add after the second paragraph:
The Am79C974 supports bus parking. When the PCI bus is idle and the system arbiter asserts GNTA without an active
REQA from the Am79C974 controller, the Am79C794 will actively drive the AD[31:00], C/BE[3:0], and PAR lines.
Page 20
Note that INTA and INTB are both open drain pins.
Page 24
Note that ATN is open drain.
Page 25
Page 30
The second sentence should read, “It is a single cycle, non-burst 8-bit, 16-bit, or 32-bit transfer which is initiated by the
host CPU.” (The original omitted “8-bit”).
Page 32
(Reprinted as page 10 of this amendment)
In Figure 6, data on the AD lines should be driven during clock 6 and the second instance of PAR should be driven
during clock 7. In each case this is one cycle earlier than what is shown in the figure.
Page 35
Line 2, change “type 15” to “type 14”.
Page 39
(Reprinted as page 11 of this amendment)
Replace the last two sentences with the following:
“For SCSI, when target aborts, INTA will not be asserted, but the ABORT bit (bit 2 of the DMA status register at offset
54h) is set. For either Ethernet or SCSI a target abort causes RTABORT (bit 12) of the status register in the appropriate
PCI configuration space to be set.” (The original stated that INTA will be asserted.)
Page 42
(Reprinted as page 12 of this amendment)
Replace the last sentence with the following:
“For SCSI, when the master aborts, INTA will not be asserted, but the ABORT bit (bit 2 of the DMA status register at
offset 54h) is set. For either Ethernet or SCSI a master abort causes RMABORT (bit 13) of the status register in the
appropriate PCI configuration space to be set.” (The original stated that INTA will be asserted.)
2
The number of each type of power pin is incorrect. The numbers should be:
— VDD/DVDD, Digital Power, 5 pins
— VDDB/VDDBS, I/O Buffer Power, 5 pins
— VSS/DVSS Digital Ground, 9 pins
— VSSB/VSSBS, I/O Buffer Ground, 11 pins
AMD
A M E N D M E N T
Am79C974
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