AM79C974KCW AMD [Advanced Micro Devices], AM79C974KCW Datasheet - Page 40
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AM79C974KCW
Manufacturer Part Number
AM79C974KCW
Description
PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems
Manufacturer
AMD [Advanced Micro Devices]
Datasheet
1.AM79C974KCW.pdf
(153 pages)
- Current page: 40 of 153
- Download datasheet (833Kb)
Master Initiated Termination
There are three scenarios besides normal completion of
a transaction where the Am79C974 controller will termi-
nate the cycles it produces on the PCI bus. These are
Preemption with and without FRAME assertion and
Master Abort.
Preemption When FRAME is Deasserted
The Am79C974 controller can generate multiple ad-
dress phases during a single bus ownership period
40
AMD
DEVSEL
FRAME
TRDY
IRDY
C/BE
REQ
GNT
PAR
CLK
AD
Figure 14. Preemption When FRAME is Deasserted
1
DEVSEL is sampled by the Am79C974 controller.
2
P R E L I M I N A R Y
3
ADDR
0111
Am79C974
4
DATA
when transferring data. FRAME is deasserted in be-
tween two address phases. While FRAME is deass-
erted, the central arbiter can remove GNT to the
Am79C974 controller at any time to service another
master. When GNT is removed, the Am79C974 control-
ler will finish the current transfer and then release the
bus. It will keep REQ asserted to regain bus ownership
as soon as possible.
BE's
PAR
5
PAR
6
7
8
18681A-18
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