AM79C974KCW AMD [Advanced Micro Devices], AM79C974KCW Datasheet - Page 29

• Manufacturer Part Number: AM79C974KCW
• Description: PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems
• Manufacturer: AMD [Advanced Micro Devices]

Slave I/O Transfers
After the Am79C974 controller is configured as I/O de-
vice (by setting IOEN in the PCI Command register), it
starts monitoring the PCI bus for access to its internal
registers. The Am79C974 controller will look for an ad-
dress that falls within its I/O address space. The
Am79C974 controller will assert DEVSEL if it detects an
address match and the access is an I/O cycle. DEVSEL
is asserted two clock cycles after the host has asserted
FRAME. The Am79C974 controller will not assert DEV-
SEL if it detects an address match, but the PCI com-
mand is not of the type I/O read or I/O write. The
DEVSEL
FRAME
TRDY
STOP
IRDY
C/BE
PAR
CLK
AD
1
ADDR
0010
2
PAR
BE's
3
4
Figure 3. Slave I/O Read
P R E L I M I N A R Y
Am79C974
5
Am79C974 controller will suspend looking for I/O cycles
while being a bus master.
Slave I/O Read
The Slave I/O Read command is used by the host CPU
to read the Am79C974’s CSRs, BCRs and EEPROM lo-
cations and SCSI and CCB registers. It is a single cycle,
non-burst 8-bit,16-bit or 32-bit transfer which is initiated
by the host CPU. The typical number of wait states
added to a slave I/O read access on the part of the
Am79C974 controller is 6 to 7 clock cycles. The
Am79C974 controller will not produce Slave I/O Read
commands while being a bus master.
6
7
8
9
DATA
10
PAR
11
18681A-7
AMD
29