ZL50130PBGA ZARLINK [Zarlink Semiconductor Inc], ZL50130PBGA Datasheet - Page 21

• Manufacturer Part Number: ZL50130PBGA
• Description: Ethernet Pseudo-Wires across a PSN
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

3.6
The Memory Management Unit handles all access to the on- and off-chip packet memory, arbitrating between the
different modules requiring access. Efficient use of memory is maintained by allocating memory in small blocks or
“granules”.
The ZL50130 includes a large amount of on-chip memory, such that for most applications, external memory will not
be required. However, for some applications there may be a requirement for external memory. Therefore the device
allows the connection of up to 8 Mbytes of synchronous ZBT SRAM.
Features include:
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3.7
The Host Interface is directly compatible with the Motorola PowerQUICC™ II microprocessor family. It provides the
host CPU with read and write access to registers, internal memory blocks, and the main on- and off-chip data
memory. The device supports dual address DMA transfers of packets to and from the CPU memory, using the
host's own DMA controller.
Features include:
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On-chip packet memory for self-contained operation
Up to 8 Mbytes of off-chip packet memory
Interfaces to bandwidth efficient ZBT SRAM devices
Operates at 100 MHz
64 bit wide data path
Supports one memory bank consisting of up to 2x32 bit devices or 1x64 bit device
Interfaces directly to PowerQUICC™ II (MPC8260) microprocessors using the GPCM
32 bit wide data bus
Allows target access to all on-chip registers and memory, and to external packet memory
DMA support, for transfer of packets to and from the host CPU
Flexible interrupt controller
Memory Management Unit
Host Interface
RFC 2819 Remote Network Monitoring MIB (for SMIv2)
RFC 2863 Interfaces Group MIB
Zarlink Semiconductor Inc.
ZL50130
21
Data Sheet