ZL50130PBGA ZARLINK [Zarlink Semiconductor Inc], ZL50130PBGA Datasheet - Page 37

• Manufacturer Part Number: ZL50130PBGA
• Description: Ethernet Pseudo-Wires across a PSN
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

4.5.2
All JTAG Interface signals are 5 V tolerant, and conform to the requirements of IEEE1149.1 (2001).
4.6
JTAG_TRST
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
IC_GND
IC_VDD_IO
Miscellaneous Inputs
Signal
Signal
JTAG Interface
I/O
I U
I U
I U
O
AF16
AD9, AF8, R5, T4, AE8
I
Table 12 - Miscellaneous Inputs Package Ball Definitions
Table 11 - JTAG Interface Package Ball Definition
AE7
AD8
AA10
AF7
AC9
Package Balls
Package Balls
Zarlink Semiconductor Inc.
ZL50130
37
Internally Connected. Tie to GND.
Internally Connected. Tie to VDD_IO.
JTAG Reset. Asynchronous
reset. In normal operation this
pin should be pulled low.
JTAG Clock - maximum
frequency is 25 MHz, typically
run at 10 MHz. In normal
operation this pin should be
pulled either high or low.
JTAG test mode select.
Synchronous to JTAG_TCK
rising edge. Used by the Test
Access Port controller to set
certain test modes.
JTAG test data input.
Synchronous to JTAG_TCK.
JTAG test data output.
Synchronous to JTAG_TCK.
Description
Description
Data Sheet