ZL50130PBGA ZARLINK [Zarlink Semiconductor Inc], ZL50130PBGA Datasheet - Page 44

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ZL50130PBGA

Manufacturer Part Number
ZL50130PBGA
Description
Ethernet Pseudo-Wires across a PSN
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
9.1.2
RXCLK period
RXCLK high wide time
RXCLK low wide time
RXCLK rise time
RXCLK fall time
RXD[3:0] setup time (RXCLK
rising edge)
RXD[3:0] hold time (RXCLK
rising edge)
RXDV input setup time
(RXCLK rising edge)
RXDV input hold time (RXCLK
rising edge)
RXER input setup time (RXCL
edge)
RXER input hold time (RXCLK
rising edge)
RXD[3:0]
MII Receive Timing
RXCLK
RXDV
RXER
Parameter
Table 19 - MII Receive Timing - 100 Mbit/s
Symbol
t
t
t
t
t
t
t
t
t
DVH
ERH
t
t
DVS
ERS
CC
CH
CR
CF
DS
DH
Figure 8 - MII Receive Timing Diagram
CL
Zarlink Semiconductor Inc.
t
t
DVS
DS
Min.
14
14
10
10
10
ZL50130
5
5
5
-
-
-
t
DH
44
t
CC
100 Mbit/s
Typ.
t
ERS
40
20
20
-
-
-
-
-
-
-
-
t
ERH
Max.
26
26
5
5
-
-
-
-
-
-
-
t
CLO
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
CHI
t
DVH
Data Sheet
Notes

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