ZL50130PBGA ZARLINK [Zarlink Semiconductor Inc], ZL50130PBGA Datasheet - Page 55

• Manufacturer Part Number: ZL50130PBGA
• Description: Ethernet Pseudo-Wires across a PSN
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

11.1.2
The MII interface passes data to and from the ZL50130 with their related transmit and receive clocks. It is therefore
recommended that the trace lengths for transmit related signals and their clock and the receive related signals and
their clock are kept to the same length. By doing this the skew between individual signals and their related clock will
be minimized.
11.1.3
Particular effort should be made to minimize crosstalk from ZL50130 outputs and ensuring fast rise time to these
inputs.
In Summary:
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11.2
The CPU_TA output signal from the ZL50130 is a critical handshake signal to the CPU that ensures the correct
completion of a bus transaction between the two devices. As the signal is critical, it is recommend that the circuit
shown in Figure 19 is implemented in systems operating above 40 MHz bus frequency to ensure robust operation
under all conditions.
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Place series termination resistors as close to the pins as possible.
minimize output capacitance.
Keep common interface traces close to the same length to avoid skew.
Protect input clocks and signals from crosstalk.
The following external logic is required to implement the circuit:
74LCX74 dual D-type flip-flop (one section of two)
74LCX08 quad AND gate (one section of four)
74LCX125 quad tri-state buffer (one section of four)
4K7 resistor x2
CPU TA Output
MAC Interface - special considerations during layout
Summary
CPU_CLK
to ZL50130
CPU_TA
from ZL50130
+3V3
Figure 19 - CPU_TA Board Circuit
4K7
R1
D
Zarlink Semiconductor Inc.
Q
ZL50130
55
CPU_CS
to ZL50130
+3V3
R2
4K7
CPU_TA
to CPU
Data Sheet