ZL50130PBGA ZARLINK [Zarlink Semiconductor Inc], ZL50130PBGA Datasheet - Page 34

• Manufacturer Part Number: ZL50130PBGA
• Description: Ethernet Pseudo-Wires across a PSN
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

CPU_CS
CPU_WE
CPU_OE
CPU_TS_ALE
CPU_SDACK1
CPU_SDACK2
Signal
I/O
I U
I
I
I
I
I
AF14
AD14
AE14
AE15
AF15
AD15
Table 8 - CPU Interface Package Ball Definition
Package Balls
Zarlink Semiconductor Inc.
ZL50130
34
CPU Chip Select. Synchronous
to rising edge of CPU_CLK and
active low. Is asserted with
CPU_TS_ALE. Must be
asserted with CPU_OE to
asynchronously enable the
CPU_DATA output during a
read, including DMA read.
CPU Write Enable.
Synchronously asserted with
respect to CPU_CLK rising
edge, and active low. Used for
CPU writes from the processor
to registers within the ZL50130.
Asserted one clock cycle after
CPU_TS_ALE
CPU Output Enable.
Synchronously asserted with
respect to CPU_CLK rising
edge, and active low. Used for
CPU reads from the processor
to registers within the ZL50130.
Asserted one clock cycle after
CPU_TS_ALE. Must be
asserted with CPU_CS to
asynchronously enable the
CPU_DATA output during a
read, including DMA read.
Synchronous input with rising
edge of CPU_CLK.
Latch Enable (ALE), active high
signal. Asserted with CPU_CS,
for a single clock cycle.
CPU/DMA 1 Acknowledge Input.
Active low synchronous to
CPU_CLK rising edge. Used to
acknowledge request from
ZL50130 for a DMA write
transaction. Only used for DMA
transfers, not for normal register
access.
CPU/DMA 2 Acknowledge Input
Active low synchronous to
CPU_CLK rising edge. Used to
acknowledge request from
ZL50130 for a DMA read
transaction. Only used for DMA
transfers, not for normal register
access.
Description
Data Sheet