M1AFS250-FGG256I Actel Corporation, M1AFS250-FGG256I Datasheet - Page 120

• Manufacturer Part Number: M1AFS250-FGG256I
• Description: Actel Fusion Family Of Mixed Signal Fpgas
• Manufacturer: Actel Corporation

Device Architecture
2- 10 4
ADC Configuration Description
The Fusion ADC can be configured to operate in 8-, 10-, or 12-bit modes, power-down after conversion,
and dynamic calibration. This is controlled by MODE[3:0], as defined in
The output of the ADC is the RESULT[11:0] signal. In 8-bit mode, the Most Significant 8 Bits
RESULT[11:4] are used as the ADC value and the Least Significant 4 Bits RESULT[3:0] are logical '0's.
In 10-bit mode, RESULT[11:2] are used the ADC value and RESULT[1:0] are logical '0's.
Table 2-41 • Mode Bits Function
The speed of the ADC depends on its internal clock, ADCCLK, which is not accessible to users. The
ADCCLK is derived from SYSCLK. Input signal TVC[7:0], Time Divider Control, determines the speed of
the ADCCLK in relationship to SYSCLK, based on
Table 2-42 • TVC Bits Function
The frequency of ADCCLK, f
The inputs to the ADC are synchronized to SYSCLK. A conversion is initiated by asserting the
ADCSTART signal on a rising edge of SYSCLK.
page 2-109
A conversion is performed in three phases. In the first phase, the analog input voltage is sampled on the
input capacitor. This phase is called sample phase. During the sample phase, the output signals BUSY
and SAMPLE change from '0' to '1', indicating the ADC is busy and sampling the analog signal. The
sample time can be controlled by input signals STC[7:0]. The sample time can be calculated by
When controlling the sample time for the ADC along with the use of Prescaler or Current Monitor or
Temperature Monitor, the minimum sample time for each must be obeyed. Refer to the corresponding
section and
Name
MODE
MODE
MODE
Name
TVC
TVC: Time Divider Control (0–255)
t
t
STC: Sample Time Control value (0–255)
ADCCLK
SYSCLK
is the period of SYSCLK
show the timing diagram for the ADC.
is the period of ADCCLK, and must be between 0.5 MHz and 10 MHz
Table 2-43
Bits
1:0
3
2
for further information.
0 – Internal calibration after every conversion; two ADCCLK cycles are used
after the conversion.
1 – No calibration after every conversion
0 – Power-down after conversion
1 – No Power-down after conversion
00 – 10-bit
01 – 12-bit
10 – 8-bit
11 – Unused
ADCCLK
t
ADCCLK
, must be within 0.5 Hz to 10 MHz.
t
sample
=
=
R e visio n 1
4
(
Bits
[7:0]
×
2
(
+
1
EQ
STC
+
TVC
Figure 2-83 on page 2-108
11.
)
×
)
Function
t
ADCCLK
×
t
SYSCLK
SYSCLK divider control
Table 2-41 on page
Function
and
Figure 2-84 on
2-104.
EQ
EQ 12
EQ 11
12.