M1AFS250-FGG256I Actel Corporation, M1AFS250-FGG256I Datasheet - Page 43

• Manufacturer Part Number: M1AFS250-FGG256I
• Description: Actel Fusion Family Of Mixed Signal Fpgas
• Manufacturer: Actel Corporation

Global Input Selections
Each global buffer, as well as the PLL reference clock, can be driven from one of the following
22):
Notes:
1. Represents the global input pins. Globals have direct access to the clock conditioning block and are not
2. Instantiate the routed clock source input as follows:
3. LVDS-based clock sources are available in the east and west banks on all Fusion devices.
Figure 2-22 • Clock Input Sources Including CLKBUF, CLKBUF_LVDS/LVPECL, and CLKINT
Each shaded box represents an
input buffer called out by the
appropriate name: INBUF or
INBUF_LVDS/LVPECL.
•
•
•
routed via the FPGA fabric. Refer to the
information.
a) Connect the output of a logic element to the clock input of the PLL, CLKDLY, or CLKINT macro.
b) Do not place a clock source I/O (INBUF or INBUF_LVPECL/LVDS) in a relevant global pin location.
Sample Pin Names
3 dedicated single-ended I/Os using a hardwired connection
2 dedicated differential I/Os using a hardwired connection
The FPGA core
GAA[0:2]: GA represents global in the northwest corner
of the device. A[0:2]: designates specific A clock source.
GAA0
GAA1
GAA2
1
1
1
+
+
"User I/O Naming Convention" section on page 2-160
R e v i s i o n 1
To Core
Actel Fusion Family of Mixed Signal FPGAs
(from FPGA core)
Routed Clock
Source for CCC
(CLKA or CLKB or CLKC)
2
(Figure 2-
for more
2- 27